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1 september 2004 dsc-5995/10 ? 2004 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. the terasync is a trademark of integrated device tech nology, inc. commercial and industrial temperature ranges 2.5 volt high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40, 131,072 x 40 idt72t4088, idt72t4098 idt72t40108, idt72t40118 features ? ? ? ? ? choose among the following memory organizations: idt72t4088 ? ? ? ? ? 16,384 x 40 idt72t4098 ? ? ? ? ? 32,768 x 40 idt72t40108 ? ? ? ? ? 65,536 x 40 idt72t40118 ? ? ? ? ? 131,072 x 40 ? up to 250mhz operating frequency or 10gbps throughput in sdr mode ? up to 110mhz operating frequency or 10gbps throughput in ddr mode ? users selectable input port to output port data rates, 500mb/s data rate -ddr to ddr -ddr to sdr -sdr to ddr -sdr to sdr ? user selectable hstl or lvttl i/os ? read enable & read clock echo outputs aid high speed operation ? ? ? ? ? 2.5v lvttl or 1.8v, 1.5v hstl port selectable input/ouput voltage ? ? ? ? ? 3.3v input tolerant ? mark & retransmit, resets read pointer to user marked position ? write chip select ( wcs ) input enables/disables write operations ? read chip select ( rcs ) synchronous to rclk ? programmable almost-empty and almost-full flags, each flag functional block diagram can default to one of four preselected offsets ? dedicated serial clock input for serial programming of flag offsets ? user selectable input and output port bus sizing -x40 in to x40 out -x40 in to x20 out -x40 in to x10 out -x20 in to x40 out -x10 in to x40 out ? auto power down minimizes standby power consumption ? master reset clears entire fifo ? partial reset clears data, but retains programmable settings ? empty and full flags signal fifo status ? select idt standard timing (using ef and ff flags) or first word fall through timing (using or and ir flags) ? output enable puts data outputs into high-impedance state ? jtag port, provided for boundary scan function ? 208 ball grid array (pbga), 17mm x 17mm, 1mm pitch ? easily expandable in depth and width ? independent read and write clocks (permit reading and writing simultaneously) ? high-performance submicron cmos technology ? industrial temperature range (-40 c to +85 c) is available input register output register ram array 16,384 x 40, 32,768 x 40 65,536 x 40 131,072 x 40 flag logic ff / ir paf ef / or pae read pointer read control logic write control logic write pointer reset logic wen wclk d 0 -d n (x40, x20, x10) sren mrs ren rclk oe q 0 -q n (x40, x20, x10) offset register prs fwft sen rt 5995 drw01 bus configuration ow fsel0 fsel1 iw mark sclk rcs jtag control (boundary scan) tck tms tdo tdi trst rsdr wcs erclk eren hstl i/0 control vref hstl bm wsdr si so
2 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 a b c d e f g h j k l m n p r t v cc v cc d34 d35 d30 tck wclk d24 d25 v cc v cc v ref d2 gnd d7 q4 gnd q0 gnd q3 v ddq gnd q7 d13 q5 d1 gnd d4 d10 d15 fsel0 d17 q9 v ddq q23 q28 ren rclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a1 ball pad corner mark rcs v ddq v ddq v ddq v ddq gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd d5 prs ow d29 d26 d18 d19 q1 q2 ef / or v ddq wen mrs iw wsdr d27 d23 d37 d32 tdi tms fwft wcs bm fsel1 rsdr d28 d20 d21 d22 d11 q37 q39 v ddq si sren eren erclk q31 q34 q18 q16 q14 v ddq q10 q12 q6 q22 q8 d31 trst tdo paf ff / ir d36 d39 d8 v cc d3 v cc d6 v ddq gnd v ddq gnd q21 v ddq q20 v ddq v cc v cc v cc v cc v ddq gnd v ddq gnd q26 v ddq q27 v ddq gnd gnd gnd v ddq v ddq v ddq q13 v ddq v ddq gnd gnd d16 d12 d14 q19 q15 q17 q11 q38 sen so pae q30 q33 q36 q29 rt oe sclk gnd v ddq v ddq v ddq gnd v cc v cc v cc v cc v cc v cc v cc v ddq gnd v ddq gnd v ddq gnd v cc v cc v cc v ddq gnd v ddq gnd v ddq q35 q32 d38 q24 q25 d33 hstl gnd d9 gnd d0 5995 drw02 pbga: 1mm pitch, 17mm x 17mm (bb208-1, order code: bb) top view pin configurations
3 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 description the idt72t4088/72t4098/72t40108/72t40118 are exceptionally deep, extremely high speed, cmos first-in-first-out (fifo) memories with the ability to read and write data on both rising and falling edges of clock. the device has a flexible x40/x20/x10 bus-matching mode and the option to select single or double data rates for input and output ports. these fifos offer several key user benefits: ? flexible x40/x20/x10 bus-matching on both read and write ports ? ability to read and write on both rising and falling edges of a clock ? user selectable single or double data rate of input and output ports ? a user selectable mark location for retransmit ? user selectable i/o structure for hstl or lvttl ? the first word data latency period, from the time the first word is written to an empty fifo to the time it can be read, is fixed and short. ? high density offerings up to 5mbit ? 10gbps throughput bus-matching double data rate fifos are particularly appropriate for network, video, telecommunications, data communications and other applica- tions that require fast data transfer on both rising and falling edges of the clock. this is a great alternative to increasing data rate without extending the width of the bus or the speed of the device. they are also effective in applications that need to buffer large amounts of data and match buses of unequal sizes. each fifo has a data input port (dn) and a data output port (qn), both of which can assume either a 40-bit, 20-bit, or a 10-bit width as determined by the state of external control pins input width (iw), output width (ow), and bus- matching (bm) pin during the master reset cycle. the input port is controlled by a write clock (wclk) input and a write enable ( wen ) input. data present on the dn data inputs can be written into the fifo on every rising and falling edge of wclk when wen is asserted and write single data rate ( wsdr ) pin held high. data can be selected to write only on the rising edges of wclk if wsdr is asserted. to guarantee functionality of the device, wen must be a controlled signal and not tied to ground. this is important because wen must be high during the time when the master reset ( mrs ) pulse is low. in addition, the wsdr pin must be tied high or low. it is not a controlled signal and cannot be changed during fifo operation. write operations can be selected for either single or double data rate mode. for single data rate operation, writing into the fifo requires the write single data rate ( wsdr ) pin to be asserted. data will be written into the fifo on the rising edge of wclk when the write enable ( wen ) is asserted. for double data rate operations, writing into the fifo requires wsdr to be deasserted. data will be written into the fifo on both rising and falling edge of wclk when wen is asserted. the output port is controlled by a read clock (rclk) input and a read enable ( ren ) input. data is read from the fifo on every rising and falling edge of rclk when ren is asserted and read single data rate ( rsdr ) pin held high. data can be selected to read only on the rising edges of rclk if rsdr is asserted. to guarantee functionality of the device, ren must be a controlled signal and not tied to ground. this is important because ren must be high during the time when the master reset ( mrs ) pulse is low. in addition, the rsdr pin must be tied high or low. it is not a controlled signal and cannot be changed during fifo operation. read operations can be selected for either single or double data rate mode. similar to the write operations, reading from the fifo in single data rate requires the read single data rate ( rsdr ) pin to be asserted. data will be read from the fifo on the rising edge of rclk when the read enable ( ren ) is asserted. for double data rate operations, reading into the fifo requires rsdr to be deasserted. data will be read out of the fifo on both rising and falling edge of rclk when and ren is asserted. both the input and output port can be selected for either 2.5v lvttl or hstl operation. this can be achieved by tying the hstl signal low for lvttl or high for hstl voltage operation. when the read port is setup for hstl mode, the read chip select ( rcs ) input also has the benefit of disabling the read port inputs, providing additional power savings. there is the option of selecting different data rates on the input and output ports of the device. there are a total of four combinations to choose from, double data rate to double data rate (ddr to ddr), ddr to single data rate (ddr to sdr), sdr to ddr, and sdr to sdr. the rates can be set up using the wsdr and rsdr pins. for example, to set up the input to output combination of ddr to sdr, wsdr will be high and rsdr will be low. read and write operations are initiated on the rising edge of rclk and wclk respectively, never on the falling edge. if ren or wen is asserted after a rising edge of clock, no read or write operations will be possible on the falling edge of that same pulse. an output enable ( oe ) input is provided for high-impedance control of the outputs. a read chip select ( rcs ) input is also provided for synchronous enable/disable of the read port control input, ren . the rcs input is synchro- nized to the read clock, and also provides high-impedance controls to the qn data outputs. when rcs is disabled, ren will be disabled internally and the data outputs will be in high-impedance. unlike the read chip select signal however, oe is not synchronous to rclk. outputs are high-impedanced shortly after a delay time when the oe transitions from low to high. the echo read enable ( eren ) and echo read clock (erclk) outputs are used to provide tighter synchronization between the data being transmitted from the qn outputs and the data being received by the input device. these output signals from the read port are required for high-speed data communi- cations. data read from the read port is available on the output bus with respect to eren and erclk, which is useful when data is being read at high-speed operations where synchronization is important. the frequencies of both the rclk and wclk signals may vary from 0 to fmax with complete independence. there are no restrictions on the frequency of one clock input with respect to another. there are two possible timing modes of operation with these devices: idt standard mode and first word fall through (fwft) mode. in idt standard mode, the first word written to an empty fifo will not appear on the data output lines unless a specific read operation is performed. a read operation, which consists of activating ren and enabling a rising rclk edge, will shift the word from internal memory to the data output lines. be aware that in double data rate (ddr) mode only the idt standard mode is available. in fwft mode, the first word written to an empty fifo is clocked directly to the data output lines after three transitions of rclk. a read operation does not have to be performed to access the first word written to the fifo. however, subsequent words written to the fifo do require a low on ren for access. the state of the fwft input during master reset determines the timing mode in use. for applications requiring more data storage capacity than a single fifo can provide, the fwft timing mode permits depth expansion by chaining fifos in series (i.e. the data outputs of one fifo are connected to the corresponding data inputs of the next). no external logic is required. these fifos have four flag pins, ef / or (empty flag or output ready), ff / ir (full flag or input ready), pae (programmable almost-empty flag), and paf (programmable almost-full flag). the ef and ff functions are selected in idt standard mode. the ir and or functions are selected in fwft mode. pae and paf are always available for use, irrespective of timing mode.
4 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 description (continued) pae and paf flags can be programmed independently to switch at any point in memory. programmable offsets mark the location within the internal memory that activates the pae and paf flags and can only be programmed serially. to program the offsets, set sen active and data can be loaded via the serial input (si) pin at the rising edge of sclk. to read out the offset registers serially, set sren active and data can be read out via the serial output (so) pin at the rising edge of sclk. four default offset settings are also provided, so that pae can be marked at a predefined number of locations from the empty boundary and the paf threshold can also be marked at similar predefined values from the full boundary. the default offset values are set during master reset by the state of the fsel0 and fsel1 pins. during master reset ( mrs ), the following events occur: the read and write pointers are set to the first location of the internal fifo memory, the fwft pin selects idt standard mode or fwft mode, the bus width configuration of the read and write port is determined by the state of iw and ow, and the default offset values for the programmable flags are set. the partial reset ( prs ) also sets the read and write pointers to the first location of the memory. however, the timing mode and the values stored in the programmable offset registers before partial reset remain unchanged. the flags are updated according to the timing mode and offsets in effect. prs is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. the timing of the pae and paf flags are synchronous to rclk and wclk, respectively. the pae flag is asserted upon the rising edge of rclk only and not wclk. similarly the paf is asserted and updated on the rising edge of wclk only and not rclk. this device includes a retransmit from mark feature that utilizes two control inputs, mark and rt (retransmit). if the mark input is enabled with respect to the rclk, the memory location being read at the point will be marked. any subsequent retransmit operation (when rt goes low), will reset the read pointer to this ?marked? location. the device can be configured with different input and output bus widths as previously stated. these rates are: x40 to x40, x40 to x20,x40 to x10, x20 to x40, and x10 to x40. if, at any time, the fifo is not actively performing an operation, the chip will automatically power down. once in the power down state, the standby supply current consumption is minimized. initiating any operation (by activating control inputs) will immediately take the device out of the power down state. a jtag test port is provided, here the fifo has fully functional boundary scan feature, compliant with ieee 1449.1 standard test access port and boundary scan architecture. the double data rate fifo has the capability of operating in either lvttl or hstl mode. hstl mode can be selected by enabling the hstl pin. both input and output ports will operate in either hstl or lvttl mode, but cannot be selected independent of one another. the idt72t4088/72t4098/72t40108/72t40118 are fabricated using idt?s high-speed submicron cmos technology.
5 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 bm i w ow write port width read port width l l l x40 x40 h l l x40 x20 h l h x40 x10 h h l x20 x40 h h h x10 x40 table 1 bus-matching configuration modes note: 1. pin status during master reset. figure 1. single device configuration signal flow diagram (x40, x20, x10) data out (q 0 - q n ) (x40, x20, x10) data in (d 0 - d n ) master reset ( mrs ) read clock (rclk) read enable ( ren ) output enable ( oe ) empty flag/output ready ( ef / or ) programmable almost-empty ( pae ) write clock (wclk) write enable ( wen ) write single data rate ( wsdr ) full flag/input ready ( ff / ir ) programmable almost-full ( paf ) idt 72t4088 72t4098 72t40108 72t40118 partial reset ( prs ) first word fall through (fwft) retransmit ( rt ) 5995 drw03 serial enable( sen ) input width (iw) output width (ow) serial clock (sclk) mark read chip select ( rcs ) rclk echo (erclk) ren echo ( eren ) write chip select ( wcs ) read single data rate ( rsdr ) serial output (so) serial input (si) serial read enable( sren ) wsdr rsdr write port width read port width h h double data rate double data rate h l double data rate single data rate l h single data rate double data rate l l single data rate single data rate table 2 data rate-matching configuration modes note: 1. pin status during master reset. 2. data rate matching can be used in conjunction with bus-matching modes.
6 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 pin description bm (1) bus-matching lvttl during master reset, this pin along with iw and ow selects the bus sizes for both write and read (k2) input ports. d 0 -d 39 data inputs hstl-lvttl data inputs for a 40-, 20-, or 10-bit bus. when in 20- or 10- bit mode, the unused input pins are in a don?t (see pin no. input care state. the data bus is sampled on both rising and falling edges of wclk when wen is enabled and table for details) ddr mode is enabled or on the rising edges of wclk only in sdr mode. ef / or empty flag/ hstl-lvttl in the idt standard mode, the ef function is selected. ef indicates whether or not the fifo memory (m14) output ready output is empty. in fwft mode, the or function is selected. or indicates whether or not there is valid data available at the outputs. erclk echo read hstl-lvttl read clock echo output, must be equal to or faster than the qn data outputs. (l16) clock output eren echo read hstl-lvttl read enable echo output, used in conjunction with erclk. (k16) enable output ff / ir full flag/ hstl-lvttl in the idt standard mode, the ff function is selected. ff indicates whether or not the fifo memory is (h3) input ready output empty. in fwft mode, the ir function is selected. ir indicates whether or not there is space available for writing to the fifo memory. fsel0 (1) flag select bit 0 lvttl during master reset, this input along with fsel1 will select the default offset values for the programmable (j3) input flags pae and paf . there are four possible settings available. fsel1 (1) flag select bit 1 l vttl during master reset, this input along with fsel0 will select the default offset values for the programmable (j2) input flags pae and paf . there are four possible settings available. fwft first word fall lvttl during master reset, selects first word fall through or idt standard mode. fwft is not available in (g2) through input ddr mode. in sdr mode, the first word will always fall through on the rising edge. hstl (1) hstl select lvttl this input pin is used to select hstl or 2.5v lvttl device operation. if hstl inputs are required, this (b7) input input must be tied high, otherwise it must be tied low and cannot toggle during operation. iw (1) input width lvttl during master reset, this pin along with ow and bm, selects the bus width of the read and write port. (k1) input mark mark read hstl-lvttl when this pin is asserted the current location of the read pointer will be marked. any subsequent retransmit (e14) pointer for input operation will reset the read pointer to this position. there is an unlimited number to times to set the mark retransmit location, but only the most recent location marked will be acknowledged. mrs master reset hstl-lvttl mrs initializes the read and write pointers to zero and sets the output registers to all zeros. during master (j1) input reset, the fifo is configured for either fwft or idt standard mode, bus-matching configurations, and programmable flag default settings. oe output enable hstl-lvttl when high, data outputs q 0 -q 39 are in high impedance. when low, the data outputs q 0 -q 39 are enabled. (g15) input no other outputs are affected by oe . ow (1) output width lvttl during master reset, this pin along with iw and bm, selects the bus width of the read and write port. (l3) input pae programmable hstl-lvttl pae goes high if the number of words in the fifo memory is greater than or equal to offset n, which is (l15) almost-empty output stored in the empty offset register. pae goes low if the number of words in the fifo memory is less than flag offset n. paf programmable hstl-lvttl paf goes high if the number of free locations in the fifo memory is more than offset m, which is stored (g3) almost-full flag output in the full offset register. paf goes low if the number of free locations in the fifo memory is less than or equal to m. prs partial reset hstl-lvttl prs initializes the read and write pointers to zero and sets the output registers to all zeros. during partial (k3) input reset, the existing mode (idt standard or fwft) and programmable flag settings are not affected. q 0 -q 39 data outputs hstl-lvttl data outputs for a 40-, 20-, or 10-bit bus. when in 20- or 10- bit mode, the unused output pins should not (see pin no. output be connected. the output data is clocked on both rising and falling edges of rclk when ren is enabled table for details) and ddr mode is enabled or on the rising edges of rclk only in sdr mode. rclk read clock hstl-lvttl input clock when used in conjunction with ren for reading data from the fifo memory and output register. (g16) input symbol & name i/o type description pin no.
7 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 pin description (continued) rcs read chip select hstl-lvttl rcs provides synchronous enable/disable control of the read port and high-impedance control of the (f14) input qn data outputs, synchronous to rclk. when using rcs the oe pin must be tied low. during master or partial reset the rcs input is don?t care, if oe is low the data outputs will be low-impedance regardless of rcs . ren read enable hstl-lvttl when low and in ddr mode, ren along with a rising and falling edge of rclk will send data in fifo (f16) input memory to the output register and read the current data in output register. in sdr mode data will only be read on the rising edge of rclk only. rsdr (1) read single data lvttl when low, this input pin sets the read port to single data clock mode. when high, the read port will operate (l2) rate input in double data clock mode. this pin must be tied either high or low and cannot toggle during operation. rt retransmit hstl-lvttl rt asserted on the rising edge of rclk initializes the read pointer to the first location in memory. ef flag (f15) input is set to low ( or to high in fwft mode). the write pointer, offset registers, and flag settings are not affected. if a mark has been set via the mark input pin, then the read pointer will initialize to the mark location when rt is asserted. sclk serial clock lvttl a rising edge of sclk will clock the serial data present on the si input into the offset registers provided (h15) input that sen is enabled. a rising edge of sclk will also read data out of the offset registers provided that sren is enabled. sen serial input hstl-lvttl sen used in conjunction with si and sclk enables serial loading of the programmable flag offsets. (j15) enable input sren serial read hstl-lvttl sren used in conjunction with so and sclk enables serial reading of the programmable flag offsets. (j16) enable input si serial input hstl-lvttl this input pin is used to load serial data into the programmable flag offsets. used in conjunction wit h sen (h16) input and sclk. so serial output hstl-lvttl this output pin is used to read data from the programmable flag offsets. used in conjunction with sren (k15) output and sclk. tck (2) jtag clock hstl-lvttl clock input for jtag function. one of four terminals required by ieee standard 1149.1-1990. test (f1) input operations of the device are synchronous to tck. data from tms and tdi are sampled on the rising edge of tck and outputs change on the falling edge of tck. if the jtag function is not used this signal needs to be tied to gnd. tdi (2) jtag test data hstl-lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan operation, (e2) input input test data serially loaded via the tdi on the rising edge of tck to either the instruction register, id register and bypass register. an internal pull-up resistor forces tdi high if left unconnected. tdo (2) jtag test data hstl-lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan operation, (f3) output output test data serially loaded output via the tdo on the falling edge of tck from either the instruction register, id register and bypass register. this output is high impedance except when shifting, while in shift- dr and shift-ir controller states. tms (2) jtag mode hstl-lvttl tms is a serial input pin. one of four terminals required by ieee standard 1149.1-1990. tms directs the (f2) select input the device through its tap controller states. an internal pull-up resistor forces tms high if left unconnected. trst (2) jtag reset hstl-lvttl trst is an asynchronous reset pin for the jtag controller. the jtag tap controller does not (e3) input automatically reset upon power-up, thus it must be reset by either this signal or by setting tms= high for five tck cycles. if the tap controller is not properly reset then the fifo outputs will always be in high- impedance. if the jtag function is used but the user does not want to use trst , then trst can be tied with mrs to ensure proper fifo operation. if the jtag function is not used then this signal needs to be tied to gnd. an internal pull-up resistor forces trst high if left unconnected. wclk write clock hstl-lvttl input clock when used in conjunction with wen for writing data into the fifo memory. (g1) input wcs write chip select hstl-lvttl the wcs pin can be regarded as a second wen input, enabling/disabling write operations. (h2) input wen write enable hstl-lvttl when low and in ddr mode, wen along with a rising and falling edge of wclk will write data into the (h1) input fifo memory. in sdr mode data will only be read on the rising edge of rclk only. symbol & name i/o type description pin no.
8 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 pin description (continued) symbol & name i/o type description pin no. wsdr (1) write single data lvttl when low, this input pin sets the write port to single data clock mode. when high, the write port will (l1) rate input operate in double data clock mode. this pin must be tied either high or low and cannot toggle during operation. v cc +2.5v supply input there are vcc supply inputs and must be connected to the 2.5v supply rail. (see below) v ddq o/p rail voltage input this pin should be tied to the desired voltage rail for providing power to the output drivers. nominally 1.5v (see below) or 1.8v for hstl, 2.5v for lvttl. gnd core ground pin input these are ground pins are for the core device and must be connected to the gnd rail. (see below) vref reference input this is a voltage reference input and must be connected to a voltage level determined in the (t3) voltage recommended dc operating conditions section. this provides the reference voltage when using hstl class inputs. if hstl class inputs are not being used, this pin must be connected to gnd. pin number table symbol name i/o type pin number d 0-39 data inputs hstl-lvttl d0-c3, d1-a4, d2-b4, d3-c4, d4-a5, d5-b5, d6-c5, d7-a6, d8-b6, d9-a7, d10-r7, d11-t7, input d12-r6, d13-t6, d14-r5, d15-t5, d16-r4, d17-t4, d18-p3, d19-r3, d20-n2, d21-p2, d22-r2, d23-n1, d24-p1, d25-r1, d26-n3, d(27-29)-m(1-3), d30-e1, d(31-33)-d(3-1), d34-c1, d(35,36)-b(1,2), d37-c2, d38-a3, d39-b3 q 0-39 data outputs hstl-lvttl q0-b10, q1-a10, q2-b11, q3-a11, q4-b12, q5-a12, q6-b13, q7-a13, q8-b14, q9-a14, q10-t14 output q11-r14, q12-t13, q13-r13, q14-t12, q15-r12, q16-t11, q17-r11, q18-t10, q19-r10, q(20,21)-c(14,15), q(22,23)-b(15,16), q24-c16, q(25-27)-d(16-14), q(28,29)-e(16,15), q(30,31)-m(15,16), q(32-34)- n(14-16), q(35-37)-p(14-16), q(38,39)-r(15,16) v cc +2.5v supply input a(1,2), c(6,7), d(4-7), k4, l4, m4, n(4-7), p(5-7), t(1,2) v ddq o/p rail voltage input a(15,16), c(10-13), d(10-13), e13, f(4,13), g(4,14), h(4,14), j14, k14, l14, m13, n(10-13), p(10-13), t(15,16) gnd ground pin input a(8,9), b(8,9), c(8,9), d(8,9), e4, g(7-10,13), h(7-10,13), j(4,7-10,13), k(7-10,13), l13, n(8,9), p(4,8,9), r(8,9), t(8,9) notes: 1. inputs should not change state after master reset. 2. these pins are for the jtag port. please refer to pages 25-28 and figures 5-7.
9 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 symbol rating commercial unit v term terminal voltage ?0.5 to +3.6 (2) v with respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?50 to +50 ma dc electrical characteristics (commercial: v cc = 2.5v 0.125v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.125v, t a = -40 c to +85 c) symbol parameter min. max. unit i li input leakage current ?10 10 a i lo output leakage current ?10 10 a v oh (5) output logic ?1? voltage, i oh = ?8 ma @v ddq = 2.5v 0.125v (lvttl) v ddq -0.4 ? v i oh = ?8 ma @v ddq = 1.8v 0.1v (ehstl) v ddq -0.4 ? v i oh = ?8 ma @v ddq = 1.5v 0.1v (hstl) v ddq -0.4 ? v v ol output logic ?0? voltage, i ol = 8 ma @v ddq = 2.5v 0.125v (lvttl) ? 0.4v v i ol = 8 ma @v ddq = 1.8v 0.1v (ehstl) ? 0.4v v i ol = 8 ma @v ddq = 1.5v 0.1v (hstl) ? 0.4v v i cc1 (1,2) active v cc current (v cc = 2.5v) i/o = lvttl ? 20 ma i/o = hstl ? 60 ma i/o = ehstl ? 60 ma i cc2 (1) standby v cc current (v cc = 2.5v) i/o = lvttl ? 10 ma i/o = hstl ? 50 ma i/o = ehstl ? 50 ma absolute maximum ratings recommended dc operating conditions notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. compliant with jedec jesd8-5. v cc terminal only. symbol parameter (1) conditions max. unit c in (2,3) input v in = 0v 10 (3) pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. 3. c in for vref is 20pf. notes: 1. both wclk and rclk toggling at 20mhz. data inputs toggling at 10mhz. wcs = high, ren or rcs = high. 2. typical i cc1 calculation : for lvttl i/o i cc1 (ma) = 0.6ma x fs, fs = wclk frequency = rclk frequency (in mhz) for hstl or ehstl i/o i cc1 (ma) = 38ma + (0.7ma x fs), fs = wclk frequency = rclk frequency (in mhz) 3. typical i ddq calculation: with data outputs in high-impedance: i ddq (ma) = 0.15ma x fs with data outputs in low-impedance: i ddq (ma) = (c l x v ddq x fs x 2n)/2000 fs = wclk frequency = rclk frequency (in mhz), v ddq = 2.5v for lvttl; 1.5v for hstl; 1.8v for ehstl, n = number of outputs switching. t a = 25c, c l = capacitive load (pf) 4. total power consumed: pt = [(v cc x i cc ) + (v ddq x i ddq )]. 5. outputs are not 3.3v tolerant. note: 1. v ref is only required for hstl or ehstl inputs. v ref should be tied low for lvttl operation. symbol parameter min. typ. max. unit v cc supply voltage 2.375 2.5 2.625 v v ddq output rail voltage for i/os 2.375 2.5 2.625 v gnd supply voltage 0 0 0 v v ih input high voltage ? lvttl 1.7 ? 3.45 v ? ehstl v ref +0.2 ? ? v ? hstl v ref +0.2 ? ? v v il input low voltage ? lvttl -0.3 ? 0.7 v ? ehstl ? ? v ref -0.2 v ? hstl ? ? v ref -0.2 v v ref voltage reference input ? ehstl 0.8 0.9 1.0 v (hstl only) ? hstl 0.68 0.75 0.9 v t a operating temperature commercial 0 ? 70 c t a operating temperature industrial -40 ? 85 c
10 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 ac electrical characteristics (1) (commercial: v cc = 2.5v 5%, t a = 0 c to +70 c;industrial: v cc = 2.5v 5%, t a = -40 c to +85 c) commercial commercial com?l & ind?l (2) commercial idt72t4088l4 idt72t4088l5 idt72t4088l6-7 idt72t4088l10 idt72t4098l4 idt72t4098l5 idt72t4098l6-7 idt72t4098l10 idt72t40108l4 idt72t40108l5 idt72t40108l6-7 idt72t40108l10 idt72t40118l4 idt72t40118l5 idt72t40118l6-7 idt72t40118l10 symbol parameter min. max. min. max. min. max. min. max. unit f s1 clock cycle frequency sdr ? 250 ? 200 ? 150 ? 100 mhz f s2 clock cycle frequency ddr ? 110 ? 100 ? 75 ? 50 mhz t a data access time 0.6 3.2 0.6 3.6 0.6 3.8 0.6 4.5 ns t aso data access serial output time 0.6 3.2 0.6 3.6 0.6 3.8 0.6 4.5 ns t clk1 clock cycle time sdr 4 ? 5 ? 6.7 ? 10 ? ns t clk2 clock cycle time ddr 9.1 ? 10 ? 13 ? 20 ? ns t clkh1 clock high time sdr 1.8 ? 2.3 ? 2.8 ? 4.5 ? ns t clkh2 clock high time ddr 4.0 ? 4.5 ? 6.0 ? 9.5 ? ns t clkl1 clock low time sdr 1.8 ? 2.3 ? 2.8 ? 4.5 ? ns t clkl2 clock low time ddr 4.0 ? 4.5 ? 6.0 ? 9.5 ? ns t ds data setup time 1.2 ? 1.5 ? 2.0 ? 3.0 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 1.2 ? 1.5 ? 2.0 ? 3.0 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t wcss wcs setup time 1.2 ? 1.5 ? 2.0 ? 3.0 ? ns t wcsh wcs hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns f c clock cycle frequency (sclk) ? 10 ? 10 ? 10 ? 10 mhz t sclk serial clock cycle 100 ? 100 ? 100 ? 100 ? ns t sckh serial clock high 45 ? 45 ? 45 ? 45 ? ns t sckl serial clock low 45 ? 45 ? 45 ? 45 ? ns t sds serial data in setup 15 ? 15 ? 15 ? 15 ? ns t sdh serial data in hold 5 ? 5 ? 5 ? 5 ? ns t sens serial enable setup 5 ? 5 ? 5 ? 5 ? ns t senh serial enable hold 5 ? 5 ? 5 ? 5 ? ns t rs reset pulse width (3) 30 ? 30 ? 30 ? 30 ? ns t rss reset setup time 15 ? 15 ? 15 ? 15 ? ns t hrss hstl reset setup time 4 ? 4 ? 4 ? 4 ? s t rsr reset recovery time 10 ? 10 ? 10 ? 10 ? ns t rsf reset to flag and output time ? 10 ? 12 ? 15 ? 15 ns t olz output enable to output in low z (4) 0?0?0?0?ns t oe output enable to output valid ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t ohz output enable to output in high z (4) ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t wff write clock to ff or ir ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t ref read clock to ef or or ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t pafs write clock to programmable almost-full flag ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t paes read clock to programmable almost-empty flag ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t erclk rclk to echo rclk output ? 3.6 ? 4 ? 4.3 ? 5 ns t clken rclk to echo ren output ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t rcslz rclk to active from high-z ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t rcshz rclk to high-z (4) ? 3.2 ? 3.6 ? 3.8 ? 4.5 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir 3.5?4?5?7?ns t skew2 skew time between rclk & wclk for ef / or & ff / ir in ddr mode 3.5?4?5?7?ns t skew3 skew time between rclk and wclk for pae and paf 4?5?6?8?ns notes: 1. all ac timings apply to both idt standard mode and first word fall through mode. 2. industrial temperature range product for the 6-7ns speed grade is available as a standard device. all other speed grades are available by special order. 3. pulse widths less than minimum values are not allowed. 4. values guaranteed by design, not currently tested.
11 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 input pulse levels 0.25 to 1.25v input rise/fall times 0.4ns input timing reference levels 0.75v output reference levels 0.75v hstl 1.5v ac test conditions figure 2b. lumped capacitive load, typical derating ac test loads figure 2a. ac test load input pulse levels 0.4 to 1.4v input rise/fall times 0.4ns input timing reference levels 0.9v output reference levels 0.9v extended hstl 1.8v ac test conditions input pulse levels gnd to 2.5v input rise/fall times 1ns input timing reference levels 1.25v output reference levels 1.25v 2.5v lvttl 2.5v ac test conditions note: 1. v ddq = 1.5v. note: 1. v ddq = 1.8v. note: 1. for lvttl v cc = v ddq . 5995 drw04 50 ? v ddq /2 i/o z 0 = 50 ? 10pf 5995 drw04a 6 5 4 3 2 1 20 30 50 80 100 200 capacitance (pf) t cd (typical, ns)
12 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 output enable & disable timing v ih oe v il t oe & t olz v cc 2 v cc 2 100mv 100mv t ohz 100mv 100mv output normally low output normally high v ol v oh v cc 2 v cc 2 5995 drw04b output enable output disable read chip select enable & disable timing v ih rcs v il t ens t enh t rcslz rclk v cc 2 v cc 2 100mv 100mv t rcshz 100mv 100mv output normally low output normally high v ol v oh v cc 2 v cc 2 5995 drw04c notes: 1. ren is high. 2. rcs is low. notes: 1. ren is high. 2. oe is low.
13 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 functional description timing modes: idt standard vs first word fall through (fwft) mode the idt72t4088/72t4098/72t40108/72t40118 support two different timing modes of operation: idt standard mode or first word fall through (fwft) mode. the selection of which mode will operate is determined during master reset, by the state of the fwft input. during master reset, if the fwft pin is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the fifo. it also uses the full flag function ( ff ) to indicate whether or not the fifo has any free space for writing. in idt standard mode, every word read from the fifo, including the first, must be requested using the read enable ( ren ) and rclk. if the fwft pin is high during master reset, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs (qn). it also uses input ready ( ir ) to indicate whether or not the fifo has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to qn after three rclk rising edges, applying ren = low is not necessary. however, subsequent words must be accessed using the read enable ( ren ) and rclk. various signals, in both inputs and outputs operate differently depending on which timing mode is in effect. idt standard mode in this mode, the status flags ff , paf , pae , and ef operate in the manner outlined in table 4. to write data into the fifo, write enable ( wen ) must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of the write clock (wclk). after the first write is performed, the empty flag ( ef ) will go high. subsequent writes will continue to fill up the fifo. the programmable almost-empty flag ( pae ) will go high after n + 1 words have been loaded into the fifo, where n is the empty offset value. the default setting for these values are listed in table 3. this parameter is also user programmable. see section on programmable flag offset loading. continuing to write data into the fifo without performing read operations will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (16,384-m) writes for the idt72t4088, (32,768-m) writes for the idt72t4098, (65,536-m) writes for the idt72t40108 and (131,072-m) writes for the idt72t40118. the offset ?m? is the full offset value. the default setting for these values are listed in table 3. this parameter is also user programmable. see the section on programmable flag offset loading. when the fifo is full, the full flag ( ff ) will go low, inhibiting further write operations. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 16,384 writes for the idt72t4088, 32,768 writes for the idt72t4098, 65,536 writes for the idt72t40108 and 131,072 writes for the idt72t40118, respectively. if the fifo is full, the first read operation will cause ff to go high. subsequent read operations will cause paf to go high at the conditions described in table 4 if further read operations occur, without write operations, pae will go low when there are n words in the fifo, where n is the empty offset value. continuing read operations will cause the fifo to become empty. then the last word has been read from the fifo, the ef will go low inhibiting further read operations. ren is ignored when the fifo is empty. when configured in idt standard mode, the ef and ff outputs are double register-buffered outputs. idt standard mode is available when the device is configured in both single data rate and double data rate mode. relevant timing diagrams for idt standard mode can be found in figure 10, 11, 12, 13, 14, 15, 16, 17, 18 and 23. first word fall through mode (fwft) in this mode, the status flags or , ir , pae , and paf operate in the manner outlined in table 5. to write data into to the fifo, wen must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of wclk. after the first write is performed, the output ready ( or ) flag will go low. subsequent writes will continue to fill up the fifo. pae will go high after n + 2 words have been loaded into the fifo, where n is the empty offset value. the default setting for these values are listed in table 3. this parameter is also user programmable. see section on programmable flag offset loading. continuing to write data into the fifo without performing read operations will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (16,385-m) writes for the idt72t4088, (32,769-m) writes for the idt72t4098, (65,537-m) writes for the idt72t40108 and (131,073-m) writes for the idt72t40118. the offset ?m? is the full offset value. the default setting for these values are listed in table 3. this parameter is also user programmable. see the section on programmable flag offset loading. when the fifo is full, the input ready ( ir ) will go low, inhibiting further write operations. if no reads are performed after a reset, ir will go low after d writes to the fifo. d = 16,385 writes for the idt72t4088, 32,769 writes for the idt72t4098, 65,537 writes for the idt72t40108 and 131,073 writes for the idt72t40118, respectively. note that the additional word in fwft mode is due to the capacity of the memory plus output register. if the fifo is full, the first read operation will cause ir to go high. subsequent read operations will cause paf to go high at the conditions described in table 5. if further read operations occur, without write operations, pae will go low when there are n words in the fifo, where n is the empty offset value. continuing read operations will cause the fifo to become empty. then the last word has been read from the fifo, the or will go high inhibiting further read operations. ren is ignored when the fifo is empty. when configured in fwft mode, the or flag output is triple register-buffered and the ir flag output is double register-buffered. fwft mode is only available when the device is configured in single data rate mode. relevant timing diagrams for idt standard mode can be found in figure 19, 20, 21, 22 and 24.
14 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 idt72t4088, 72t4098, 72t40108, 72t40118 fsel1 fsel0 offsets n,m h h 255 l h 127 hl63 ll7 table 3 default programmable flag offsets notes: 1. n = empty offset for pae . 2. m = full offset for paf . programming flag offsets full and empty flag offset values are user programmable. the idt72t4088/ 72t4098/72t40108/72t40118 have internal registers for these offsets. there are four selectable default offset values during master reset. these offset values are shown in table 3. the offset values can also be programmed serially into the fifo. to load offset values, set sen low and the rising edge of sclk will idt72t4088 idt72t4098 0 0 1 to n (1) (16,384-m) to 16,383 16,384 idt72t40118 0 table 4 ? status flags for idt standard mode table 5 ? status flags for fwft mode f f p a f p a e e f hh ll hh l h hhhh hl hh l l hh number of words in fifo 5995 drw05 idt72t40108 0 (8,193) to (16,384-(m+1)) (32,768-m) to 32,767 32,768 (16,385) to (32,768-(m+1)) (65,536-m) to 65,535 65,536 (32,769) to (65,536-(m+1)) (131,072-m) to 131,071 131,072 (65,537) to (131,072-(m+1)) idt72t4088 idt72t4098 0 0 1 to n+1 (1) (16,385-m) to 16,384 16,385 idt72t40118 0 i r p a f p a e o r lh lh lh l l l hhl llhl h l hl number of words in fifo idt72t40108 0 (8,194) to (16,385-(m+1)) (32,769-m) to 32,768 32,769 (16,386) to (32,769-(m+1)) (65,537-m) to 65,536 65,537 (32,770) to (65,537-(m+1)) (131,073-m) to 131,072 131,073 (65,538) to (131,073-(m+1)) 1 to n (1) 1 to n (1) 1 to n (1) 1 to n+1 (1) 1 to n+1 (1) 1 to n+1 (1) note: 1. see table 3 for values for n, m. note: 1. see table 3 for values for n, m. 2. fwft mode available only in single data rate mode. load data from the si input into the offset registers. sclk runs at a nominal speed of 10mhz at the maximum. the programming sequence starts with one bit for each sclk rising edge, starting with the empty offset lsb and ending with the full offset msb. the total number of bits per device is listed in figure 3, programmable flag offset programming sequence . see figure 25, loading of programmable flag registers , for the timing diagram for this mode. the pae and paf can show a valid status only after the complete set of bits (for all offset registers) has been entered. the registers can be reprogrammed as long as the complete set of new offset bits is entered. in addition to loading offset values into the fifo, it is also possible to read the current offset values. similar to loading offset values, set sren low and the rising edge of sclk will send data from the offset registers out to the so output port. when initializing a read to the offset registers, data will be read starting from the first location in the register, regardless of where it was last read. figure 3, programmable flag offset programming sequence , summarizes the control pins and sequence for programming offset registers and reading and writing into the fifo. the offset registers may be programmed (and reprogrammed) any time after master reset. valid programming ranges are from 0 to d-1.
15 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 3. programmable flag offset programming sequence notes: 1. the programming sequence applies to both idt standard and fwft modes. 2. when the input or output ports are in ddr mode, the depth is reduced by half but the overall density remains the same. for example, the idt72t4088 in sdr mode is 16,384 x 40 = 655,360, in ddr mode the configuration becomes 8,192 x 80 = 655,360. in both cases, the total density are the sam e. wclk rclk x w s d r x x r s d r x x s e n 0 1x s r e n 1 0 idt72t4088 idt72t4098 idt72t40108 idt72t40118 sclk x 5995 drw06 x w e n 1 1 r e n 1 1 in sdr mode x 11 xx write memory (ddr) x 01 x 01 xx write memory (sdr) x 01 x 11 xx read memory (ddr) x 10 x 10 xx read memory (sdr) x 10 x xx no operation x 11 x x x 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) serial write to registers: 28 bits for the idt72t4088 30 bits for the idt72t4098 32 bits for the idt72t40108 34 bits for the idt72t40118 serial write to registers: in ddr mode 26 bits for the idt72t4088 28 bits for the idt72t4098 30 bits for the idt72t40108 32 bits for the idt 72t40118 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) in sdr mode 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) serial read from registers: 28 bits for the idt72t4088 30 bits for the idt72t4098 32 bits for the idt72t40108 34 bits for the idt72t40118 in ddr mode 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) serial read from registers: 26 bits for the idt72t4088 28 bits for the idt72t4098 30 bits for the idt72t40108 32 bits for the idt72t40118
16 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 retransmit from mark operation the retransmit from mark feature allows fifo data to be read repeatedly starting at a user-selected position. the fifo is first put into retransmit mode that will ?mark? a beginning word and also set a pointer that will prevent ongoing fifo write operations from over-writing retransmit data. the retrans- mit data can be read repeatedly any number of times from the ?marked? position. the fifo can be taken out of retransmit mode at any time to allow normal device operation. the ?mark? position can be selected any number of times, each selection over-writing the previous mark location. in double data rate, data is always marked in pairs. that is, the unit of data read on the rising and falling edge of wclk. if the data marked was read on the falling edge of rclk, then the marked data will be the unit of data read from the rising and falling edge of that particular rclk edge. refer to figure 23, retransmit from mark in double data rate mode , for the timing diagram in this mode. retransmit operation is available in both idt standard and fwft modes. during idt standard mode the fifo is put into retransmit mode by a low- to-high transition on rclk when the mark input is high and ef is high. the rising rclk edge marks the data present in the fifo output register as the first retransmit data. again, the data is marked in pairs. thus if the data marked was read on the falling edge of rclk, the first part of retransmit will read out the data read on the rising edge of rclk, followed by the data on the falling edge (the marked data). the fifo remains in retransmit mode until a rising edge on rclk occurs while mark is low. once a marked location has been set, a retransmit can be initiated by a rising edge on rclk while the retransmit input ( rt ) is low. ren must be high (reads disabled) before bringing rt low. the device indicates the start of retransmit setup by setting ef low, also preventing reads. when ef goes high, retransmit setup is complete and read operations may begin starting with the first unit of data at the mark location. since idt standard mode is selected, every word read including the first ?marked? word following a re- transmit setup requires a low on ren . note, write operations may continue as normal during all retransmit functions, however write operations to the ?marked? location will be prevented. see figure 23, retransmit from mark in double data rate mode , for the relevant timing diagram. during fwft mode the fifo is put into retransmit mode by a rising rclk edge when the mark input is high and or is low. the rising rclk edge marks the data present in the fifo output register as the first retransmit data. the data is marked in pairs. the fifo remains in retransmit mode until a rising rclk edge occurs while mark is low. once a marked location has been set, a retransmit can be initiated by a rising rclk edge while the retransmit input ( rt ) is low. ren must be high (reads disabled) before bringing rt low. the device indicates the start of retransmit setup by setting or high, preventing read operations. when or goes low, retransmit setup is complete and on the next rising rclk edge ( rt goes high), the contents of the first retransmit location are loaded onto the output register. since fwft mode is selected, the first word appears on the outputs regardless of ren , a low on ren is not required for the first word. reading all subsequent words requires a low on ren to enable the rising rclk edge. see figure 24, retransmit from mark (fwft mode) for the relevant timing diagram. before a retransmit can be performed, there must be at least 1280 bits (or 160 bytes) of data between the write pointer and mark location. that is, 40 bits x32 for the x40 mode, 20 bits x64 for the x20 mode, and 10 bits x128 for the x10 mode. also, once the mark is set, the write pointer will not increment past the marked location, preventing overwrites of retransmit data. hstl/lvttl i/o this device supports both lvttl and hstl logic levels on the input and output signals. if lvttl is desired, a low on the hstl pin will set the inputs and outputs to lvttl mode. if hstl is desired, a high on the hstl pin will set the inputs and outputs to hstl mode. vref is the input voltage reference used in hstl mode. typically a logic high in hstl would be vref + 0.2v and a logic low would be vref ? 0.2v. table 6 illustrates which pins are and are not associated with this feature. note that all ?static pins? must be tied to vcc or gnd. these pins are lvttl only and are purely device configuration pins. hstl select static pins high = hstl lvttl only low = lvttl write port read port signal pins static pins dn (i/p) qn (o/p) ef / or (o/p) sclk (i/p) trst (i/p) iw (i/p) wclk (i/p) rclk (i/p) paf (o/p) si (i/p) tdi (i/p) ow (i/p) wen (i/p) ren (i/p) pae (o/p) so (o/p) tdo (o/p) bm ((i/p) wcs (i/p) rcs (i/p) ff / ir (o/p) mrs (i/p) sen (i/p) hstl (i/p) mark (i/p) erclk (o/p) prs (i/p) sren (i/p) fsel1 (i/p) oe (i/p) eren (o/p) tck (i/p) fsel0 (i/p) rt (i/p) tms (i/p) fwft (i/p) wsdr (i/p) rsdr (i/p) table 6 i/o configuration
17 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 signal description inputs: data in (d0 ? dn) (d 0 ? d 39 ) are data inputs for the 40-bit wide data, (d 0 ? d 19 ) are data inputs for the 20-bit wide data, or (d 0 ? d 9 ) are data inputs for 10-bit wide data. controls: master reset ( mrs ) a master reset is accomplished whenever the mrs input is taken to a low state. this operation sets the internal read and write pointers to the first location of the ram array. pae will go low and paf will go high. if fwft is low during master reset then idt standard mode along with ef and ff are selected. ef will go low and ff will go high, if fwft is high, then the first word fall through (fwft) mode, along with ir and or are selected. or will go high and ir will go low. all control settings such as ow, iw, bm, wsdr , rsdr , fsel0 and fsel1 are defined during the master reset cycle. during a master reset the output register is initialized to all zeros. a master reset is required after power up before a write operation can take place. mrs is asynchronous. see figure 8, master reset timing , for the relevant timing diagram. partial reset ( prs ) a partial reset is accomplished whenever the prs input is taken to a low state. as in the case of the master reset, the internal read and write pointers are set to the first location of the ram array. pae goes low and paf goes high. whichever mode was active at the time of partial reset will remain active after partial reset. if idt standard mode is active, then ff will go high and ef will go low. if the first word fall through mode is active, then or will go high and ir will go low. following partial reset, all values held in the offset registers remain un- changed. the output register is initialized to all zeroes. prs is asynchronous. partial reset is useful for resetting the read and write pointers to zero without affecting the values of the programmable flag offsets and the timing mode of the fifo. see figure 9, partial reset timing , for the relevant timing diagram. retransmit ( rt ) the retransmit ( rt ) input is used in conjunction with the mark input. together they provide a means by which data previously read out of the fifo can be reread any number of times. when the retransmit operation is selected (i.e. after data has been marked), a rising edge on rclk while rt is low will reset the read pointer back to the memory location set by the user via the mark input. if idt standard mode has been selected, the ef flag will go low on the rising edge of rclk that retransmit was initiated (i.e. rising edge of rclk while rt is low). ef will go back to high on the next rising edge of rclk, which signifies that retransmit setup is complete. the next read operation will access data from the ?marked? memory location. subsequent retransmit operations may be performed, each time the read pointer returning to the ?marked? location. see figure 23, retransmit from mark in double data rate mode (idt standard mode) for the relevant timing diagram. if fwft mode has been selected, the or flag will go high on the rising edge of rclk that retransmit was initiated. or will return low on the next rising edge of rclk, which signifies that retransmit setup is complete. under fwft mode, the contents in the marked memory location will be loaded onto the output register on the next rising edge of rclk. to access all subsequent data, a read operation will be required. subsequent retransmit operations may be performed, each time the read pointer returning to the ?marked? location. see figure 24, retransmit from mark (fwft mode) for the relevant timing diagram. mark the mark input is used to select retransmit mode of operation. on a rising edge of rclk while mark is high will mark the memory location of the data currently present on the output register, in addition placing the device in retransmit mode. note, there must be a minimum of 1280 bits (or 160 bytes) of data between the write pointer and mark location. that is, 40 bits x32 for the x40 mode, 20 bits x64 for the x20 mode, and 10 bits x128 for the x10 mode. also, once the mark is set, the write pointer will not increment past the ?marked? location until the mark is deasserted. this prevents ?overwriting? of retransmit data. the mark input must remain high during the whole period of retransmit mode, a rising edge of rclk while mark is low will take the device out of retransmit mode and into normal mode. any number of mark locations can be set during fifo operation, only the last marked location taking effect. once a mark location has been set the write pointer cannot be incremented past this marked location. during retransmit mode write operations to the device may continue without hindrance. first word fall through (fwft) during master reset, the state of the fwft input determines whether the device will operate in idt standard mode or first word fall through (fwft) mode. if, at the time of master reset, fwft is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the fifo memory. it also uses the full flag function ( ff ) to indicate whether or not the fifo memory has any free space for writing. in idt standard mode, every word read from the fifo, including the first, must be requested using the read enable ( ren ) and rclk. if, at the time of master reset, fwft is high, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the outputs (qn) to be read. it also uses input ready ( ir ) to indicate whether or not the fifo memory has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to qn after three rclk rising edges, bringing ren low is not necessary. subsequent words must be accessed using the read enable ( ren ) and rclk. note that fwft mode can only be used when the device is configured to single data rate (sdr) mode. write clock (wclk) a write cycle is initiated on the rising and/or falling edge of the wclk input. if the write single data rate ( wsdr ) pin is selected, data will be written only on the rising edge of wclk, provided that wen and wcs are low. if the wsdr is not selected, data will be written on both the rising and falling edge of wclk, provided that wen and wcs are low. data setup and hold times must be met with respect to the low-to-high transition of the wclk. it is permissible to stop the wclk. note that while wclk is idle, the ff , ir , and paf flags will not be updated. the write and read clocks can either be independent or coincident.
18 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 write enable ( wen ) when the wen input is low, data may be loaded into the fifo ram array on the rising edge of every wclk cycle if the device is not full. data is stored in the ram array sequentially and independently of any ongoing read opera- tion. when wen is high, no new data is written in the ram array on each wclk cycle. to prevent data overflow in the idt standard mode, ff will go low, inhibiting further write operations. upon the completion of a valid read cycle, ff will go high, allowing a write to occur. the ff is updated by two wclk cycles + t skew after the rclk cycle. to prevent data overflow in the fwft mode, ir will go high, inhibiting further write operations. upon the completion of a valid read cycle, ir will go low, allowing a write to occur. the ir flag is updated by two wclk cycles + t skew after the valid rclk cycle. wen is ignored when the fifo is full in either idt standard mode or fwft. write single data rate ( wsdr ) when the write single data rate pin is low, the write port will be set to single data rate mode. in this mode, all write operations are based only on the rising edge of wclk, provided that wen and wcs are low. when wsdr is high, the read port will be set to double data rate mode. in this mode, all write operations are based on both the rising and falling edge of wclk, provided that wen and wcs are low, on the rising edge of wclk. read clock (rclk) a read cycle is initiated on the rising and/or falling edge of the rclk input. if the read single data rate ( rsdr ) pin is selected, data will be read only on the rising edge of rclk, provided that ren and rcs are low. if the rsdr is not selected, data will be read on both the rising and falling edge of wclk, provided that ren and rcs are low, on the rising edge of rclk. setup and hold times must be met with respect to the low-to-high transition of the rclk. it is permissible to stop the rclk. note that while rclk is idle, the ef / or and pae flags will not be updated. write and read clocks can be inde- pendent or coincident. read enable ( ren ) when read enable is low, data is loaded from the ram array into the output register on the rising edge of every rclk cycle if the device is not empty. when the ren input is high, the output register holds the previous data and no new data is loaded into the output register. the data outputs q0-qn maintain the previous data value. in idt standard mode, every word accessed at qn, including the first word written to an empty fifo, must be requested using ren provided that the read chip select ( rcs ) is low. when the last word has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. ren is ignored when the fifo is empty. once a write is performed, ef will go high allowing a read to occur. both rcs and ren must be active low for data to be read out on the rising edge of rclk. in fwft mode, the first word written to an empty fifo automatically goes to the outputs qn, on the third valid low-to-high transition of rclk + t skew after the first write. ren and rcs do not need to be asserted low for the first word to fall through to the output register. all subsequent words require that a read operation to be executed using ren and rcs . the low-to-high transition of rclk after the last word has been read from the fifo will make output ready ( or ) go high with a true read (rclk with ren and rcs low), inhibiting further read operations. ren is ignored when the fifo is empty. read single data rate ( rsdr ) when the read single data rate pin is low, the read port will be set to single data rate mode. in this mode, all read operations are based only on the rising edge of rclk, provided that ren and rcs are low. when rsdr is high, the read port will be set to double data rate mode. in this mode, all read operations are based on both the rising and falling edge of rclk, provided that ren and rcs are low, on the rising edge of rclk. serial clock (sclk) the serial clock is used to load and read data in the programmable offset registers. data from the serial input (si) can be loaded into the offset registers on the rising edge of sclk provided that sen is low. data can be read from the offset registers via the serial output (so) on the rising edge of sclk provided that sren is low. the serial clock can operate at a maximum frequency of 10mhz and its parameters are different than the fifo system clock. serial enable ( sen ) the sen input is an enable used for serial programming of the program- mable offset registers. it is used in conjunction with si and sclk when pro- gramming the offset registers. when sen is low, data at the serial in (si) input can be loaded into the offset register, one bit for each low-to-high transition of sclk. when sen is high, the offset registers retain the previous settings and no offsets are loaded. sen functions the same way in both idt standard and fwft modes. serial read enable ( sren ) the sren output is an enable used for reading the value of the program- mable offset registers. it is used in conjunction with si and sclk when reading from the offset registers. when sren is low, data can be read out of the offset register from the so output, one bit for each low-to-high transition of sclk. when sren is high, the reading of the offset registers will stop. when- ever sren is activated values in the offset registers are read starting from the first location in the offset registers and not from where the last offset value was read. sren functions the same way in both idt standard and fwft modes. serial in (si) this pin acts as a serial input for loading pae and paf offsets into the programmable offset registers. it is used in conjunction with the serial clock (sclk) and the serial enable ( sen ). data from this input can be loaded into the offset register, one bit for each low-to-high transition of sclk provided that sen is low. serial out (so) this pin acts as a serial output for reading the values of the pae and paf offsets in the programmable offset registers. it is used in conjunction with the serial clock (sclk) and the serial enable output ( sren ). data from the offset register can be read out using this pin, one-bit for each low-to-high transition of sclk provided that sren is low.
19 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 output enable ( oe ) when output enable is low, the parallel output buffers receive data from the output register. when oe is high, the output data bus (qn) goes into a high-impedance state. during master or partial reset the oe is the only input that can place the output data bus into high-impedance. during reset the rcs input can be high or low and has no effect on the output data bus. read chip select ( rcs ) the read chip select input provides synchronous control of the read output port. when rcs goes low, the next rising edge of rclk causes the qn outputs to go to the low-impedance state. when rcs goes high, the next rclk rising edge causes the qn outputs to return to high-impedance. during a master or partial reset the rcs input has no effect on the qn output bus, oe is the only input that provides high-impedance control of the qn outputs. if oe is low, the qn data outputs will be low-impedance regardless of rcs until the first rising edge of rclk after a reset is complete. then if rcs is high the data outputs will go to high-impedance. the rcs input does not effect the operation of the flags. for example, when the first word is written to an empty fifo, the ef will still go from low to high based on a rising edge of rclk, regardless of the state of the rcs input. also, when operating the fifo in fwft mode the first word written to an empty fifo will still be clocked through to the output register based on rclk, regardless of the state of rcs . for this reason the user should pay extra attention when a data word is written to an empty fifo in fwft mode. if rcs is high when an empty fifo is written into, the first word will fall through to the output register but will not be available on the qn outputs because they are in high-impedance. the user must take rcs active low to access this first word, placing the output bus in low-impedance. ren must remain high for at least one cycle after rcs has gone low. a rising edge of rclk with rcs and ren low will read out the next word. care must be taken so as not to lose the first word written to an empty fifo when rcs is high. refer to figure 22, rcs and ren read operation (fwft mode). the rcs pin must also be active (low) in order to perform a retransmit. see figure 18 for read cycle and read chip select timing (idt standard mode). see figure 21 for read cycle and read chip select timing (fwft mode). write chip select ( wcs ) the wcs disables all write port inputs (data only) if it is held high. to perform normal operations on the write port, the wcs must be enabled. hstl select (hstl) the inputs that were listed in table 6 can be setup to be either hstl or lvttl. if hstl is high, then hstl operation of those signals will be se- lected. if hstl is low , then lvttl will be selected. bus-matching (bm, iw, ow) the pins bm, iw, and ow are used to define the input and output bus widths. during master reset, the state of these pins is used to configure the device bus sizes. see table 1 for control settings. all flags will operate on the word/byte size boundary as defined by the selection of bus width. see table 7 for bus-matching write to read ratio. flag select bits (fsel0 and fsel1) these pins will select the four default offset values for the pae and paf flags during master reset. the four possible settings are listed on table 3. note that the status of these inputs should not change after master reset. outputs: data out (q0-q39) (q0 ? q39) are data outputs for 40-bit wide data, (q0 ? q19) are data outputs for 20-bit wide data, or (q0 ? q9) are data outputs for 10-bit wide data. full flag ( ff / ir ) this is a dual-purpose pin. in idt standard mode, the full flag ( ff ) function is selected. when the fifo is full, ff will go low, inhibiting further write operations. when ff is high, the fifo is not full. if no reads are performed after a reset (either mrs or prs ), ff will go low after d writes to the fifo (d = 16,384 for the idt72t4088, 32,768 for the idt72t4098, 65,536 for the idt72t40108, 131,072 for the idt72t40118. see figure 10, write cycle and full flag timing (idt standard mode ), for the relevant timing information. in fwft mode, the input ready ( ir ) function is selected. ir goes low when memory space is available for writing in data. when there is no longer any free space left, ir goes high, inhibiting further write operations. if no reads are performed after a reset (either mrs or prs ), ir will go high after d writes to the fifo (d = 16,385 for the idt72t4088, 32,769 for the idt72t4098, 65,537 for the idt72t40108, 131,073 for the idt72t40118). see figure 19, write timing (fwft mode ), for the relevant timing information. the ir status not only measures the contents of the fifo memory, but also counts the presence of a word in the output register. thus, in fwft mode, the total number of writes necessary to deassert ir is one greater than needed to assert ff in idt standard mode. ff / ir is synchronous and updated on the rising edge of wclk. ff / ir are double register-buffered outputs. note, when the device is in retransmit mode, this flag is a comparison of the write pointer to the ?marked? location. this differs from normal mode where this flag is a comparison of the write pointer to the read pointer. empty flag ( ef / or ) this is a dual-purpose pin. in the idt standard mode, the empty flag ( ef ) function is selected. when the fifo is empty, ef will go low, inhibiting further read operations. when ef is high, the fifo is not empty. see figure 12, read cycle, empty flag and first word latency timing (idt standard mode ), for the relevant timing information. in fwft mode, the output ready ( or ) function is selected. or goes low at the same time that the first word written to an empty fifo appears valid on the outputs. or stays low after the rclk low to high transition that shifts the last word from the fifo memory to the outputs. or goes high only with a true read (rclk with ren = low). the previous data stays at the outputs, indicating the last word was read. further data reads are inhibited until or goes low again. see figure 20, read timing (fwft mode ), for the relevant timing information. ef / or is synchronous and updated on the rising edge of rclk. in idt standard mode, ef is a double register-buffered output. in fwft mode, or is a triple register-buffered output. programmable almost-full flag ( paf ) the programmable almost-full flag ( paf ) will go low when the fifo reaches the almost-full condition. in idt standard mode, if no reads are performed after reset ( mrs ), paf will go low after (d - m) words are written to the fifo. the paf will go low after (16,384-m) writes for the idt72t4088, (32,768-m) writes for the idt72t4098, (65,536-m) writes for the idt72t40108, (131,072-m) writes for the idt72t40118. the offset ?m? is the full offset value. the default setting for this value is listed in table 3.
20 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 in fwft mode, the paf will go low after (16,385-m) writes for the idt72t4088, (32,769-m) writes for the idt72t4098, (65,537-m) writes for the idt72t40108, (131,073-m) writes for the idt72t40118. where m is the full offset value. the default setting for this value is listed in table 3. see figure 29, programmable almost-full flag timing (idt standard and fwft mode ), for the relevant timing information. note, when the device is in retransmit mode, this flag is a comparison of the write pointer to the ?marked? location. this differs from normal mode where this flag is a comparison of the write pointer to the read pointer. programmable almost-empty flag ( pae ) the programmable almost-empty flag ( pae ) will go low when the fifo reaches the almost-empty condition. in idt standard mode, pae will go low when there are n words or less in the fifo. the offset ?n? is the empty offset value. the default setting for this value is stated in the footnote of table 3. in fwft mode, the pae will go low when there are n+1 words or less in the fifo. the default setting for this value is stated in table 3. see figure 30, programmable almost-empty flag timing (idt standard and fwft mode ), for the relevant timing information. echo read clock (erclk) the echo read clock output is provided in both hstl and lvttl mode, selectable via hstl. the erclk is a free-running clock output, it will always follow the rclk input regardless of ren and rcs . the erclk output follows the rclk input with an associated delay. this delay provides the user with a more effective read clock source when reading data from the qn outputs. this is especially helpful at high speeds when variables within the device may cause changes in the data access times. these variations in access time maybe caused by ambient temperature, sup- ply voltage, or device characteristics. the erclk output also compensates for any trace length delays between the qn data outputs and receiving de- vices inputs. any variations effecting the data access time will also have a corresponding effect on the erclk output produced by the fifo device, therefore the erclk output level transitions should always be at the same position in time relative to the data outputs. note, that erclk is guaranteed by design to be slower than the slowest qn, data output. refer to figure 4, echo read clock and data output relationship , figure 27, echo read clock & read enable operation in double data rate mode and figure 28, echo rclk & echo ren operation for timing information. echo read enable ( eren ) the echo read enable output is provided in both hstl and lvttl mode, selectable via hstl. the eren output is provided to be used in conjunction with the erclk output and provides the reading device with a more effective scheme for reading data from the qn output port at high speeds. the eren output is controlled by internal logic that behaves as follows: the eren output is active low for the rclk cycle that a new word is read out of the fifo. that is, a rising edge of rclk will cause eren to go active, low if both ren and rcs are active, low and the fifo is not empty. figure 4. echo read clock and data output relationship notes: 1. ren is low. 2. t erclk > t a , guaranteed by design. 3. qslowest is the data output with the slowest access time, t a . 4. time, t d is greater than zero, guaranteed by design. 5. ren = rcs = oe = 0. 5995 drw07 erclk t a q slowest (3) rclk t erclk t erclk t a t d t d
21 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 table 7 bus-matching write to read ratio one write to one read (1:1) configuration wsdr rsdr bm iw ow hhl l l ddr write clock x40 data in ddr read clock x40 data out positive edge 1 d[39:0] <= lw1 positive edge 1 q[39:0] <= lw1 negative edge 1 d[39:0] <= lw2 negative edge 1 q[39:0] <= lw2 x40 ddr input to x40 ddr output configuration wsdr rsdr bm iw ow lllll sdr write clock x40 data in sdr read clock x40 data out positive edge 1 d[39:0] <= lw1 positive edge 1 q[39:0] <= lw1 x40 sdr input to x40 sdr output configuration wsdr rsdr bm iw ow lhhll x40 sdr input to x20 ddr output x20 ddr input to x40 sdr output one write to two read (1:2) configuration wsdr rsdr bm iw ow hllll x40 ddr input to x40 sdr output configuration wsdr rsdr bm iw ow hhhl l ddr write clock x40 data in ddr read clock x20 data out positive edge 1 d[39:20] <= lw1 positive edge 1 q[19:0] <= lw1 d[19:0] <= lw2 negative edge 1 q[19:0] <= lw2 negative edge 1 d[39:20] <= lw3 positive edge 2 q[19:0] <= lw3 d[19:0] <= lw4 negative edge 2 q[19:0] <= lw4 x40 ddr input to x20 ddr output sdr write clock x40 data in ddr read clock x20 data out positive edge 1 d[39:20] <= w1 positive edge 1 q[19:0] <= w1 d[19:0] <= w2 negative edge 1 q[19:0] <= w2 ddr write clock x20 data in sdr read clock x40 data out positive edge 1 d[19:0] <= w1 positive edge 1 q[39:20] <= w1 negative edge 1 d[19:0] <= w2 q[19:0] <= w2 ddr write clock x40 data in sdr read clock x40 data out positive edge 1 d[39:0] <= lw1 positive edge 1 q[39:0] <= lw1 negative edge 1 d[39:0] <= lw2 positive edge 2 q[39:0] <= lw1 configuration wsdr rsdr bm iw ow llhll x40 sdr input to x20 sdr output sdr write clock x40 data in sdr read clock x20 data out positive edge 1 d[39:20] <= lw1 positive edge 1 q[19:0] <= lw1 d[19:0] <= lw2 positive edge 2 q[19:0] <= lw2 configuration wsdr rsdr bm iw ow lhhlh sdr write clock x40 data in ddr read clock x10 data out positive edge 1 d[39:30] <= b1 positive edge 1 q[9:0] <= b1 d[29:20] <= b2 negative edge 1 q[9:0] <= b2 d[19:10] <= b3 positive edge 2 q[9:0] <= b3 d[9:0] <= b4 negative edge 2 q[9:0] <= b4 x40 sdr input to x10 ddr output configuration wsdr rsdr bm iw ow hlhhl
22 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 table 7 bus-matching write to read ratio (continued) one write to four read (1:4) configuration wsdr rsdr bm iw ow hlhll x40 ddr input to x20 sdr output one write to eight read (1:8) configuration wsdr rsdr bm iw ow hlhlh x40 ddr input to x10 sdr output ddr write clock x40 data in sdr read clock x20 data out positive edge 1 d[39:20] <= lw1 positive edge 1 q[19:0] <= lw1 d[19:0] <= lw2 positive edge 2 q[19:0] <= lw2 negative edge 1 d[39:20] <= lw3 positive edge 3 q[19:0] <= lw3 d[19:0] <= lw4 positive edge 4 q[19:0] <= lw4 configuration wsdr rsdr bm iw ow llhlh x40 sdr input to x10 sdr output sdr write clock x40 data in sdr read clock x10 data out positive edge 1 d[39:30] <= b1 positive edge 1 q[9:0] <= b1 d[29:20] <= b2 positive edge 2 q[9:0] <= b2 d[19:10] <= b3 positive edge 3 q[9:0] <= b3 d[9:0] <= b4 positive edge 4 q[9:0] <= b4 configuration wsdr rsdr bm iw ow hhhlh x40 ddr input to x10 ddr output ddr write clock x40 data in sdr read clock x10 data out positive edge 1 d[39:30] <= b1 positive edge 1 q[9:0] <= b1 d[29:20] <= b2 negaitive edge 1 q[9:0] <= b2 d[19:10] <= b3 positive edge 2 q[9:0] <= b3 d[9:0] <= b4 negaitive edge 2 q[9:0] <= b4 negative edge 1 d[39:30] <= b5 positive edge 3 q[9:0] <= b5 d[29:20] <= b6 negaitive edge 3 q[9:0] <= b6 d[19:10] <= b7 positive edge 4 q[9:0] <= b7 d[9:0] <= b8 negaitive edge 4 q[9:0] <= b8 ddr write clock x40 data in sdr read clock x10 data out positive edge 1 d[39:30] <= b1 positive edge 1 q[9:0] <= b1 d[29:20] <= b2 positive edge 2 q[9:0] <= b2 d[19:10] <= b3 positive edge 3 q[9:0] <= b3 d[9:0] <= b4 positive edge 4 q[9:0] <= b4 negative edge 1 d[39:30] <= b5 positive edge 5 q[9:0] <= b5 d[29:20] <= b6 positive edge 6 q[9:0] <= b6 d[19:10] <= b7 positive edge 7 q[9:0] <= b7 d[9:0] <= b8 positive edge 8 q[9:0] <= b8
23 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 table 7 bus-matching write to read ratio (continued) two write to one read (2:1) configuration wsdr rsdr bm iw ow lhlll x40 sdr input to x40 ddr output sdr write clock x40 data in ddr read clock x40 data out positive edge 1 d[39:0] <= lw1 positive edge 1 q[39:0] <= lw1 positive edge 2 d[39:0] <= lw2 negative edge 1 q[39:0] <= lw2 configuration wsdr rsdr bm iw ow hhhhl x20 ddr input to x40 ddr output ddr write clock x20 data in ddr read clock x40 data out positive edge 1 d[19:0] <= w1 positive edge 1 q[39:20] <= w1 negative edge 1 d[19:0] <= w2 q[19:0] <= w2 positive edge 2 d[19:0] <= w3 negative edge 1 q[39:20] <= w3 negative edge 2 d[19:0] <= w4 q[19:0] <= w4 configuration wsdr rsdr bm iw ow llhhl x20 sdr input to x40 sdr output sdr write clock x20 data in sdr read clock x40 data out positive edge 1 d[19:0] <= w1 positive edge 1 q[39:20] <= w1 positive edge 2 d[19:0] <= w2 q[19:0] <= w2 configuration wsdr rsdr bm iw ow hlhhh x10 ddr input to x40 sdr output ddr write clock x10 data in sdr read clock x40 data out positive edge 1 d[9:0] <= b1 positive edge 1 q[39:30] <= b1 negative edge 1 d[9:0] <= b2 q[29:20] <= b2 positive edge 2 d[9:0] <= b3 q[19:10] <= b3 negative edge 2 d[9:0] <= b4 q[9:0] <= b4 four write to one read (4:1) configuration wsdr rsdr bm iw ow lhhhl x20 sdr input to x40 ddr output sdr write clock x20 data in ddr read clock x40 data out positive edge 1 d[19:0] <= w1 positive edge 1 q[39:20] <= w1 positive edge 2 d[19:0] <= w2 q[19:0] <= w2 positive edge 3 d[19:0] <= w3 negative edge 1 q[39:20] <= w3 positive edge 4 d[19:0] <= w4 q[19:0] <= w4 configuration wsdr rsdr bm iw ow hhhhh x10 ddr input to x40 ddr output ddr write clock x10 data in ddr read clock x40 data out positive edge 1 d[9:0] <= b1 positive edge 1 q[39:30] <= b1 negative edge 1 d[9:0] <= b2 q[29:20] <= b2 positive edge 2 d[9:0] <= b3 q[19:10] <= b3 negative edge 2 d[9:0] <= b4 q[9:0] <= b4 positive edge 3 d[9:0] <= b5 negative edge 2 q[39:30] <= b5 negative edge 3 d[9:0] <= b6 q[29:20] <= b6 positive edge 4 d[9:0] <= b7 q[19:10] <= b7 negative edge 4 d[9:0] <= b8 q[9:0] <= b8 configuration wsdr rsdr bm iw ow llhhh x10 sdr input to x40 sdr output sdr write clock x10 data in sdr read clock x40 data out positive edge 1 d[9:0] <= b1 positive edge 1 q[39:30] <= b1 positive edge 2 d[9:0] <= b2 q[29:20] <= b2 positive edge 3 d[9:0] <= b3 q[19:10] <= b3 positive edge 4 d[9:0] <= b4 q[9:0] <= b4
24 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 table 7 bus-matching write to read ratio (continued) eight write to one read (8:1) configuration wsdr rsdr bm iw ow lhhhh x10 sdr input to x40 ddr output sdr write clock x10 data in ddr read clock x40 data out positive edge 1 d[9:0] <= b1 positive edge q[39:30] <= b1 positive edge 2 d[9:0] <= b2 q[29:20] <= b2 positive edge 3 d[9:0] <= b3 q[19:10] <= b3 positive edge 4 d[9:0] <= b4 q[9:0] <= b4 positive edge 5 d[9:0] <= b5 negative edge q[39:30] <= b5 positive edge 6 d[9:0] <= b6 q[29:20] <= b6 positive edge 7 d[9:0] <= b7 q[19:10] <= b7 positive edge 8 d[9:0] <= b8 q[9:0] <= b8 table 8 t skew measurement data port status flags t skew measurement configuration ddr input ef & pae negative edge wclk to to positive edge rclk ddr output ff & paf negative edge rclk to positive edge wclk ddr input ef & pae negative edge wclk to to positive edge rclk sdr output ff & paf positive edge rclk to positive edge wclk sdr input ef & pae positive edge wclk to to positive edge rclk ddr output ff & paf negative edge rclk to positive edge wclk sdr input ef & pae positive edge wclk to to positive edge rclk sdr output ff & paf positive edge rclk to positive edge wclk
25 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 5. standard jtag timing system interface parameters parameter symbol test conditions min. max. units jtag clock input period t tck - 100 - ns jtag clock high t tckhigh -40-ns jtag clock low t tcklow -40-ns jtag clock rise time t tckrise --5 (1) ns jtag clock fall time t tckfall --5 (1) ns jtag reset t rst -50-ns jtag reset recovery t rsr -50-ns jtag ac electrical characteristics (v cc = 2.5v 5%; tcase = 0 c to +85 c) idt72t4088 idt72t4098 idt72t40108 idt72t40118 parameter symbol test conditions min. max. units data output t do (1) -20ns data output hold t doh (1) 0-ns data input t ds t rise=3ns 10 - ns t dh t fall=3ns 10 - note: 1. 50pf loading on external output signals. jtag timing specification note: 1. guaranteed by design. t 4 t 3 tdo tdo tdi/ tms tck trst t do notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tckfall t4 = t tckrise t5 = trst (reset pulse width) t6 = trsr (reset recovery) 5995 drw08 t 5 t 6 t 1 t 2 t tck t dh t ds
26 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 jtag interface five additional pins (tdi, tdo, tms, tck and trst ) are provided to support the jtag boundary scan interface. the idt72t4088/72t4098/ 72t40108/72t40118 incorporates the necessary tap controller and modified pad cells to implement the jtag facility. note that idt provides appropriate boundary scan description language program files for these devices. the standard jtag interface consists of four basic elements: ? test access port (tap) ? tap controller ? instruction register (ir) ? data register port (dr) the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the figure below shows the standard boundary-scan architecture figure 6. boundary scan architecture test access port (tap) the tap interface is a general-purpose port that provides access to the internal of the processor. it consists of four input ports (tclk, tms, tdi, trst ) and one output port (tdo). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and update of data. t a p tap cont- roller mux deviceid reg. boundary scan reg. bypass reg. clkdr, shiftdr updatedr tdo tdi tms tclk trst clklr, shiftlr updatelr instruction register instruction decode control signals 5995 drw09
27 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 7. tap controller state diagram test-logic reset run-test/ idle 1 0 0 select- dr-scan select- ir-scan 1 1 1 capture-ir 0 capture-dr 0 0 exit1-dr 1 pause-dr 0 exit2-dr 1 update-dr 1 exit1-ir 1 exit2-ir 1 update-ir 1 1 0 1 1 1 5995 drw10 0 shift-dr 0 0 0 shift-ir 0 0 pause-ir 0 1 input = tms 0 0 1 refer to the ieee standard test access port specification (ieee std. 1149.1) for the full state diagram all state transitions within the tap controller occur at the rising edge of the tclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. the tap controller takes precedence over the fifo memory and must be reset after power up of the device. see trst description for more details on tap controller reset. test-logic-reset all test logic is disabled in this controller state enabling the normal operation of the ic. the tap controller state machine is designed in such a way that, no matter what the initial state of the controller is, the test-logic-reset state can be entered by holding tms at high and pulsing tck five times. this is the reason why the test reset (trst) pin is optional. run-test-idle in this controller state, the test logic in the ic is active only if certain instructions are present. for example, if an instruction activates the self test, then it will be executed when the controller enters this state. the test logic in the ic is idles otherwise. select-dr-scan this is a controller state where the decision to enter the data path or the select-ir-scan state is made. select-ir-scan this is a controller state where the decision to enter the instruction path is made. the controller can return to the test-logic-reset state other wise. capture-ir in this controller state, the shift register bank in the instruction register parallel loads a pattern of fixed values on the rising edge of tck. the last two significant bits are always required to be ?01?. shift-ir in this controller state, the instruction register gets connected between tdi and tdo, and the captured pattern gets shifted on each rising edge of tck. the instruction available on the tdi pin is also shifted in to the instruction register. exit1-ir this is a controller state where a decision to enter either the pause- ir state or update-ir state is made. pause-ir this state is provided in order to allow the shifting of instruction register to be temporarily halted. exit2-dr this is a controller state where a decision to enter either the shift- ir state or update-ir state is made. update-ir in this controller state, the instruction in the instruction register is latched in to the latch bank of the instruction register on every falling edge of tck. this instruction also becomes the current instruction once it is latched. capture-dr in this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of tck. shift-dr, exit1-dr, pause-dr, exit2-dr and update-dr these controller states are similar to the shift-ir, exit1-ir, pause-ir, exit2-ir and update-ir states in the instruction path. notes: 1. five consecutive tck cycles with tms = 1 will reset the tap. 2. tap controller does not automatically reset upon power-up. the user must provide a reset to the tap controller (either by trst or tms). 3. tap controller must be reset before normal fifo operations can begin.
28 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 the instruction register the instruction register allows an instruction to be shifted in serially into the processor at the rising edge of tclk. the instruction is used to select the test to be performed, or the test data register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting process when the tap controller is at update- ir state. the instruction register must contain 4 bit instruction register-based cells which can hold instruction data. these mandatory cells are located nearest the serial outputs they are the least significant bits. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary scan register allows serial data tdi be loaded in to or read out of the processor input/output ports. the boundary scan register is a part of the ieee 1149.1-1990 standard jtag implementation. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the idt72t4088/72t4098/72t40108/72t40118, the part number field contains the following values: idt72t4088/4098/40108/40118 jtag device identification register 31(msb) 28 27 12 11 1 0(lsb) version (4 bits) part number (16-bit) manufacturer id (11-bit) 0x0 0x33 1 jtag instruction register the instruction register allows instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4 bit field (i.e.ir3, ir2, ir1, ir0) to decode 16 different possible instructions. instructions are decoded as follows. hex instruction function value 0x02 idcode select chip identification data register 0x01 sample/preload select boundary scan register 0x03 hi-impedance jtag 0x0f bypass select bypass register table 8. jtag instruction register decoding the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). idcode the optional idcode instruction allows the ic to remain in its functional mode and selects the optional device identification register to be connected between tdi and tdo. the device identification register is a 32-bit shift register containing information regarding the ic manufacturer, device type, and version code. accessing the device identification register does not interfere with the operation of the ic. also, access to the device identification register should be immediately available, via a tap data-scan operation, after power-up of the ic or after the tap has been reset using the optional trst pin or by otherwise moving to the test-logic-reset state. sample/preload the required sample/preload instruction allows the ic to remain in a normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the ic. high-impedance the optional high-impedance instruction sets all outputs (including two-state as well as three-state types) of an ic to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the ic outputs. bypass the required bypass instruction allows the ic to remain in a normal functional mode and selects the one-bit bypass register to be connected between tdi and tdo. the bypass instruction allows serial data to be transferred through the ic from tdi to tdo without affecting the operation of the ic. extest the required extest instruction is not available for this device. device part# field idt72t4088 04a3 idt72t4098 04a2 idt72t40108 04a1 idt72t40118 04a0
29 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 8. master reset timing notes: 1. during master reset the high-impedance control of the qn data outputs is provided by oe only, rcs can be high or low until the first rising edge of rclk after master reset is complete. 2. the status of these pins are latched in when the master reset pulse is low. 5995 drw11 rt sen t rsf t rsf oe = high oe = low pae paf q 0 - q n t rsf ef / or ff / ir t rsf t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = low, ff = high if fwft = high, ir = low t rss t rss sren t rss t rs mrs t rsr ren t rss fwft (2) t rsr t rsr wen fsel0 (2) , fsel1 ow (2) , iw, bm t rss t rss t rss t rss t hrss hstl (2) wsdr (2) t rsr t rss rsdr (2) t rsr t rss
30 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 9. partial reset timing note: 1. during partial reset the high-impedance control of the qn data outputs is provided by oe only, rcs can be high or low until the first rising edge of rclk after master reset is complete. t rs prs t rsr ren t rss 5995 drw12 t rsr wen rt sen t rsf t rsf oe = high oe = low pae paf q 0 - q n t rsf ef / or ff / ir t rsf t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = low, ff = high if fwft = high, ir = low t rss t rss t rss sren t rss
31 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 10. write cycle and full flag timing (idt standard mode) notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high (after one wclk cycle plus t wff ). if the time between the rising edge of the rclk and the rising edge of the wclk is less than t skew1 , then the ff deassertion may be delayed one extra wclk cycle. 2. oe = low, ef = high. 3. wcs = low. 4. wclk must be free running for ff to update. d 0 - d 39 wen rclk ren t enh t enh q 0 - q 39 data read next data read t skew1 (1) 5995 drw13 wclk no write 1 2 1 2 no write t wff t a t ens t ens (1) t ds t a d x t dh t clk1 t clkh1 ff rcs t ens t rcslz t wff t skew1 t clkl1 d x+1 t wff t wff t ds t dh
32 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 11. write cycle and full flag timing in double data rate mode (idt standard mode) notes: 1. t skew2 is the minimum time between a falling rclk edge and a rising wclk edge to guarantee that ff will go high (after one wclk cycle plus t wff ). if the time between the falling edge of the rclk and the rising edge of wclk is less than t skew2 , then ff deassertion may be delayed one extra wclk cycle. 2. oe = low, ef = high. 3. wcs = low, rcs = low, wsdr = high and rsdr = high. 4. wclk must be free running for ff to update. data read q 0 -q39 5995 drw14 t a 12 no write d 0- d39 rclk wclk wen ff t clkl2 t clkh2 t clk2 t skew2 (1) 12 t skew2 (1) ren no write dx t ds t ds t dh dx+1 t dh dx+2 dx+3 t wff t wff t wff t wff t enh t ens t enh t ens t a data in output register next data read next data t a t a next data read
33 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 12. read cycle, output enable, empty flag and first data word latency (idt standard mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high (after one rclk cycle plus t ref ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef deassertion may be delayed one extra rclk cycle. 2. first data word latency = t skew1 + 1*t rclk + t ref. 3. rcs is low. 4. rclk must be free running for ef to update. 5995 drw15 d 0 - d 39 t ds t dh d 0 d 1 t ds t dh no operation rclk ren ef t clk1 t enh t ref t a t olz q 0 - q 39 oe wclk (1) t skew1 wen t ens t ens t enh 1 2 t olz no operation last word d 0 d 1 t ens t enh t ohz last word t ref t enh t ens t a t a t ref t ens t enh wcs t oe t wcss t wcs h t clkh1 t clkl1
34 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 13. read cycle, output enable, empty flag and first data word latency in double data rate mode (idt standard mode) notes: 1. t skew2 is the minimum time between a falling wclk edge and a rising rclk edge to guarantee that ef will go high (after one rclk cycle plus t ref ). if the time between the falling edge of wclk and the rising edge of rclk is less than t skew2 , then ef deassertion may be delayed one extra rclk cycle. 2. ren = low. 3. first data word latency = t skew1 + 1*t rclk + t ref . 4. rcs = low, wsdr = high and rsdr = high. 5. rclk must be free running for ef to update. t olz t ref t ref d n d n d 0 t a d 1 t ohz t olz q 0- q 39 ef oe wclk wen d 0 -d 39 5995 drw16 d 0 d 1 t dh t ds t ds t dh t ens t enh t ref t a rclk 12 t skew2 (1) t clk2 t clkh2 t oe t a wcs t wcss t wcsh t a d n - 1 no read no read no read no read t clkl2
35 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 14. read cycle, empty flag and first data word latency in x40ddr to x10sdr with bus-matching and rate-matching (idt sta ndard mode) rclk ef wen ren wcs t ens t skew2 (1) d0-d39 t ds w 0 - w 3 q0-q9 wclk t enh twc sh t wcss w 4 - w 7 t dh t ds t dh 12 t ref t ens t a t a t a t a t a w0 w1 w2 t a t a t a w3 w4 w5 w6 w7 t enh t ref previous data in ouput register 5995 drw17 notes: 1. t skew2 is the minimum time between a falling wclk edge and a rising rclk edge to guarantee that ef will go high (after one rclk cycle plus t ref ). if the time between the falling edge of wclk and the rising edge of rclk is less than t skew2 , then ef deassertion may be delayed one extra rclk cycle. 2. ren = low. 3. first data word latency = t skew1 + 1*t rclk + t ref . 4. rcs = low, wsdr = high and rsdr = high. 5. rclk must be free running for ef to update.
36 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 15. read cycle and empty flag in x20sdr to x40ddr with bus-matching and rate-matching (idt standard mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high (after one rclk cycle plus t ref ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef deassertion may be delayed one extra rclk cycle. 2. oe = low. 3. first data word latency = t skew1 + 1*t rclk + t ref . 4. rcs = low, wcs = low, wsdr = low and rsdr = high. 5. rclk must be free running for ef to update. q 0- q 39 t skew (1) wclk rclk ren 12 wen t ref ef d 0 -d 19 5995 drw18 t ref t ref last word last 40-bit word t ens t enh w 0 w 1 w 2 w 3 t enh t ens w 0 -w 1 t a t a t a t a t ds t dh t ds t dh t ds t dh t dh t ds t clk2 t clkh2 t clkl2 previous data t enh no read w 2 -w 3
37 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 16. write cycle and full flag timing in x20ddr to x40sdr with bus-matching and rate-matching (idt standard mode) wclk ff wen rcs t ens t skew1 (1) q 0 -q 39 rclk t enh t ens 1 2 t wff d 0 -d 19 ren t rcslz t a t ds t ds t dh t dh t wff t skew1 (1) t ens t enh t a 1 2 t wff t ds t ds t dh t dh t clk2 t clkh2 t clkl2 no write no write t wff data read next data read wx wx+1 wx+2 wx+3 5995 drw19 notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high (after one wclk cycle plus t wff ). if the time between the rising edge of the rclk and the rising edge of the wclk is less than t skew1 , then the ff deassertion may be delayed one extra wclk cycle. 2. ld = high, oe = low, ef = high. 3. wcs = low. 4. wclk must be free running for ff to update.
38 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 17. write cycle and full flag in x40sdr to x20ddr with bus-matching and rate-matching (idt standard mode) wclk ff wen rcs t ens q0-q19 rclk t enh t ens 1 2 t wff d0-d39 ren t rcslz t a t ds t dh t ens t enh t a 1 2 t ds t ds t dh t dh t clk1 no write no write t wff data read next data read wx wx+2 wx+3 t a t ds t dh wx+1 t clkh1 t clkh1 t wff t a t skew2 (1) t wff t ens t rcshz data read next data read 5995 drw20 t skew2 (1) notes: 1. t skew2 is the minimum time between a falling rclk edge and a rising wclk edge to guarantee that ff will go high (after one wclk cycle plus t wff ). if the time between the falling edge of the rclk and the rising edge of wclk is less than t skew2 , then ff deassertion may be delayed one extra wclk cycle. 2. oe = low, ef = high. 3. wcs = low, rcs = low, wsdr = high and rsdr = high. 4. wclk must be free running for ff to update.
39 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 18. read cycle and read chip select (idt standard mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high (after one rclk cycle plus t ref ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef deassertion may be delayed one extra rclk cycle. 2. first data word latency = t skew1 + 1*t rclk + t ref. 3. oe is low. 4. rclk must be free running for ef to update. rclk ren 1 2 5995 drw21 rcs q0 - qn wclk wen dn t ens last data d x t ens t ens t ens ef t a t ref t ref t rcslz last data-1 t rcshz t rcslz t a t rcshz t skew1 (1) t enh t ens t dh t ds t enh
40 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 19. write timing (fwft mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that or will go low after two rclk cycles plus t ref . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then or assertion may be delayed one extra rclk cycle. 2. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high after one rclk cycle plus t paes . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then the pae deassertion may be delayed one extra rclk cycle. 3. oe = low 4. n = pae offset, m = paf offset and d = maximum fifo depth. 5. d = 16,385 for idt72t4088, 32,769 for idt72t4098, 65,537 for idt72t40108, 131,073 for idt72t40118. 6. first data word latency = t skew1 + 2*t rclk + t ref. w 1 w 2 w 4 w [n +2] w [d-m-1] w [d-m-2] w [d-1] w d w [n+3] w [n+4] w [d-m] w [d-m+1] wclk wen d0 - dn rclk t dh t ds t skew1 (1) ren q0 - qn paf pae ir t ds t ds t ds t skew2 t a t ref or t paes t pafs t wff w [d-m+2] w 1 t enh 5995 drw22 previous data in output register (2) w 3 1 2 3 1 d-1 2 +1 ] [ w d-1 +2 ] [ w 2 d-1 +3 ] [ w 2 1 2 t ens rcs t rcslz t ens
41 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 20. read timing (fwft mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that or will go low after two rclk cycles plus t ref . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then or assertion may be delayed one extra rclk cycle. 2. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high after one rclk cycle plus t paes . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then the pae deassertion may be delayed one extra rclk cycle. 3. oe = low 4. n = pae offset, m = paf offset and d = maximum fifo depth. 5. d = 16,385 for idt72t4088, 32,769 for idt72t4098, 65,537 for idt72t40108, 131,073 for idt72t40118. 6. first data word latency = t skew1 + 2*t rclk + t ref. wclk 12 wen d0 - dn rclk t ens ren q0 - qn paf pae ir or w 1 w 1 w 2 w 3 w m+2 w [m+3] t ohz t skew1 t enh t ds t dh t oe t a t a t a t pafs t wff t wff t ens oe t skew2 w d 5995 drw23 t paes w [d-n] w [d-n-1] t a t a t ref w [d-1] w d t a w [d-n+1] w [m+4] w [d-n+2] (1) (2) t ens d-1 + 1 ] [ w 2 d-1 + 2 ] [ w 2 1
42 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 21. read cycle and read chip select timing (fwft mode) notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ir will go low after one wclk cycle plus t wff . if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then the ir assertion may be delayed one extra wclk cycle. 2. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that paf will go high after one wclk cycle plus t pafs . if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then the paf deassertion may be delayed one extra wclk cycle. 3. n = pae offset, m = paf offset and d = maximum fifo depth. 4. d = 16,385 for idt72t4088, 32,769 for idt72t4098, 65,537 for idt72t40108, 131,073 for idt72t40118. 5. oe = low. 6. rclk must be free running for ef to update. wclk 12 wen d0 - dn rclk ren q0 - qn paf pae ir or w 1 w 2 w 3 w m+2 w [m+3] t rcshz t skew1 t enh t ds t dh t a t a t pafs t wff t wff t ens rcs t skew2 w d 5995 drw24 t paes w [d-n] w [d-n-1] t a t a w [d-1] w d t a w [d-n+1] w [m+4] w [d-n+2] (1) (2) t ens 1 t ens t rcslz t ens t ref d-1 + 1 ] [ w 2 d-1 + 2 ] [ w 2 t enh
43 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 22 . rcs and ren read operation (fwft mode) notes: 1. it is very important that the ren be held high for at least one cycle after rcs has gone low. if ren goes low on the same cycle as rcs or earlier, then word, w1 will be lost, word, w2 will be read on the output when the bus goes to low-z. 2. the 1st word will fall through to the output register regardless of ren and rcs . however, subsequent reads require that both ren and rcs be active, low. 3. rcs functions similarly to oe , when rcs is high the read pointer will not increment. wclk rclk ren qn 12 wen 3 t ens t enh t ens t ens t ens t enh t ens t ref t ref rcs or t rcslz w1 w2 t rcshz t rcslz t a w2 t skew t ens t enh w2 dn t dh t ds t dh t ds w1 1st word falls through to o/p register on this cycle 5995 drw25 high-z
44 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 23 . retransmit from mark in double data rate mode (idt standard mode) notes: 1. retransmit setup is complete when ef returns high. 2. oe = low; rcs = low. 3. rt must be high when reading from fifo. 4. once mark is set, the write pointer will not increment past the ?marked? location, preventing overwrites of retransmit data. 5. before a ?mark? can be set there must be at least 160 bytes of data between the write pointer and read pointer locations. (16 0 bytes = 16 words = 8 long words). 6. rclk must be free running for ef to update. 7. a transition in the pae flag may not occur until one rclk cycle later than shown. 8. in ddr mode the mark function will ?mark? words only on even word boundaries (i.e. rising edge of rclk). q 0- qn wclk rclk ren paf t clkl2 t clkh2 t clk2 t a w mk mark t a t a t a w mk+2 t a t a w mk+3 w mk+4 w mk+5 w mk+6 w mk+n rt ef pae t ens t enh t ref t ref t ens 1 2 t a t paes (7) t a t a t a w mk w mk+1 w mk+2 t skew2 1 2 t pafs 5995 drw26 t enh t ens t ens w mk+1
45 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 24. retransmit from mark (fwft mode) notes: 1. retransmit setup is complete when or returns low. 2. oe = low; rcs = low. 3. rt must be high when reading from fifo. 4. once mark is set, the write pointer will not increment past the ?marked? location, preventing overwrites of retransmit data. 5. before a ?mark? can be set there must be at least 160 bytes of data between the write pointer and read pointer locations. (16 0 bytes = 16 words = 8 long words). 6. rclk must be free running for ef to update. 7. a transition in the pae flag may not occur until one rclk cycle later than shown. t ref t ens t enh 5995 drw27 t ens w mk-1 wclk rclk ren rt or paf pae q n 12 1 t pafs t ref 2 wen t ens t a t ens w mk w mk+1 t a t a w mk+n t a w mk+1 w mk+2 t a t ens mark t enh t ens t paes (7) t a t skew2 w mk t a
46 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 25. loading of programmable flag registers (idt standard and fwft modes) note: 1. in sdr mode, x = 14 for the idt72t4088, x = 15 for the idt72t4098, x = 16 for the idt72t40108, x = 17 for the idt72t40118. 2. in ddr mode, x = 13 for the idt72t4088, x = 14 for the idt72t4098, x = 15 for the idt72t70108, x = 16 for the idt72t40118. sclk sen si 5995 drw28 empty offset full offset bit x (1) t sens t sds t senh bit x (1) bit 1 t enh t sdh t sclk t sckh t sckl bit 1 figure 26. reading of programmable flag registers (idt standard and fwft modes) note: 1. in sdr mode, x = 14 for the idt72t4088, x = 15 for the idt72t4098, x = 16 for the idt72t40108, x = 17 for the idt72t40118. 2. in ddr mode, x = 13 for the idt72t4088, x = 14 for the idt72t4098, x = 15 for the idt72t40108, x = 16 for the idt72t40118. 3. offset register values are always read starting from the first location in the offset register upon initiating sren . sclk sren so 5995 drw29 bit 0 empty offset full offset bit x (1) t sens t soa t senh bit x (1) t enh t soa t sclk t sckh t sckl bit 0
47 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 27. echo read clock & read enable operation in double data rate mode (idt standard mode only) notes: 1. the eren output is ?or gated? to rcs and ren and will follow these inputs provided that the fifo is not empty. if the fifo is empty, eren will go high to indicate that there is no new word available. 2. the eren output is synchronous to rclk. 3. oe = low. 4. the truth table for eren is shown below: rclk ren eren erclk ef rcs t ens t ref t erclk t enh qn t ens t enh t clken t clken t clken t clken t olz t a t a t clken t a t olz t olz t a t a t a t a t a w d-10 w d-9 w d-8 w d-6 w d-5 w d-4 w d-3 w d-2 last word w d 5995 drw30 t clken t a w d-7 w d-6 t a w d-1 t ens no read no read rclk ef rcs ren eren 1000 1011 1101 1111 0xx1
48 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 figure 28. echo rclk and echo ren operation (fwft mode only) note: 1. the o/p register is the internal output register. its contents are available on the qn output bus only when rcs and oe are both active, low, that is the bus is not in high- impedance state. 2. oe is low. cycle: a&b. at this point the fifo is empty, or is high. rcs and ren are both disabled, the output bus is high-impedance. c. word wn+1 falls through to the output register, or goes active, low. rcs is high, therefore the qn outputs are high-impedance. eren goes low to indicate that a new word has been placed on the output register. d. eren goes high, no new word has been placed on the output register on this cycle. e. no operation. f. rcs is low on this cycle, therefore the qn outputs go to low-impedance and the contents of the output register (wn+1) are made ava ilable. note: in fwft mode is important to take rcs active low at least one cycle ahead of ren , this ensures the word (wn+1) currently in the output register is made available for at least one cycle. g. ren goes active low, this reads out the second word, wn+2. eren goes active low to indicate a new word has been placed into the output register. h. word wn+3 is read out, eren remains active, low indicating a new word has been read out. note: wn+3 is the last word in the fifo. i. this is the next enabled read after the last word, wn+3 has been read out. or flag goes high and eren goes high to indicate that there is no new word available. 3. oe is low. 4. the truth table for eren is shown below: qn o/p reg. t a t ref or 5995 drw31 t rcslz ren t ens t enh rcs t ens rclk a b c d e f g h i w n+1 wclk wen d0 - dn t skew1 t ens t ds t enh w n+2 w n+3 erclk eren t clken t clken t clken t clken w n+1 w n+2 w n+3 t a t ref w n+1 w n+2 w n+3 t a w n last word t a t a t dh t dh t dh t ds t ds 1 2 t erclk high-z rclk or rcs ren eren 0000 0011 0101 0111 1xx1
49 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 notes: 1. m = paf offset. 2. d = maximum fifo depth. in idt standard mode: d=16,384 for the idt72t4088, 32,768 for the idt72t4098, 65,536 for the idt72t40108, 131,072 for the idt72t40118. in fwft mode: d=16,385 for the idt72t4088, 32,769 for the idt72t4098, 65,537 for the idt72t40108, 131,073 for the idt72t40118. 3. paf is asserted and updated on the rising edge of wclk only. 4. t skew3 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that paf will go high (after one wclk cycle plus t pafs ). if the time between the rising edge of rclk and the rising edge of wclk is less than t skew3 , then the paf deassertion time may be delayed one extra wclk cycle. 5. rcs = low. figure 29. programmable almost-full flag timing (idt standard and fwft modes) notes: 1. n = pae offset. 2. for idt standard mode. 3. for fwft mode. 4. pae is asserted and updated on the rising edge of rclk only. 5. t skew3 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high (after one rclk cycle plus t paes ). if the time between the rising edge of wclk and the rising edge of rclk is less than t skew3 , then the pae deassertion may be delayed one extra rclk cycle. 5. pae is asserted and updated on the rising edge of rclk only. 6. rcs = low. figure 30. programmable almost-empty flag timing (idt standard and fwft modes) wclk wen paf rclk ren 5995 drw32 1 2 12 d-(m+1) words in fifo (2) d - m words in fifo (2) d - (m +1) words in fifo (2) t enh t ens t pafs t ens t enh t clkl1 t skew3 (3) t pafs t clkh1 wclk wen pae rclk 12 12 ren 5995 drw33 n + 1 words in fifo (2) , n + 2 words in fifo (3) t ens t skew3 (4) t enh t paes n words in fifo (2) , n + 1 words in fifo (3) t paes n words in fifo (2) , n + 1 words in fifo (3) t ens t enh t clkh1 t clkl1
50 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 optional configurations width expansion configuration word width may be increased simply by connecting together the control signals of multiple devices. status flags can be detected from any one device. the exceptions are the ef and ff functions in idt standard mode and the ir and or functions in fwft mode. because of variations in skew between rclk and wclk, it is possible for ef / ff deassertion and ir / or assertion to vary by one cycle between fifos. in idt standard mode, such problems can be avoided by creating composite flags, that is, anding ef of every fifo, and separately anding ff of every fifo. in fwft mode, composite flags can be created by oring or of every fifo, and separately oring ir of every fifo. figure 31 demonstrates a width expansion using two idt72t4088/ 72t4098/72t40108/72t40118 devices. d 0 - d 40 from each device form a 80- bit wide input bus and q 0 -q 39 from each device form a 80-bit wide output bus. any word width can be attained by adding additional idt72t4088/72t4098/ 72t40108/72t40118 devices. notes: 1. use an and gate in idt standard mode, an or gate in fwft mode. 2. do not connect any output control signals directly together. 3. fifo #1 and fifo #2 must be the same depth, but may be different word widths. figure 31. block diagram of 16,384 x 80, 32,768 x 80, 65,536 x 80, 131,072 x 80 width expansion write clock (wclk) m + n mn master reset ( mrs ) read clock (rclk) data out n m + n write enable ( wen ) full flag/input ready ( ff / ir ) programmable ( paf ) programmable ( pae ) empty flag/output ready ( ef / or ) #2 output enable ( oe ) read enable ( ren ) m idt 72t4088 72t4098 72t40108 72t40118 empty flag/output ready ( ef / or ) #1 partial reset ( prs ) 5995 drw34 full flag/input ready ( ff / ir ) #2 first word fall through (fwft) retransmit ( rt ) #1 fifo #2 gate (1) gate (1) d 0 - d m data in d m+1 - d n q 0 - qm q m+1 - q n fifo #1 idt 72t4088 72t4098 72t40108 72t40118 read chip select ( rcs ) serial clock (sclk)
51 commercial and industrial temperature ranges idt72t4088/98/108/118 2.5v high-speed terasync? ddr/sdr fifo 40-bit configuration 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 september 21, 2004 depth expansion configuration in single data rate (fwft mode only) the idt72t4088 can easily be adapted to applications requiring depths greater than 16,384, 32,768 for the idt72t4098, 65,536 for the idt72t40108, 131,072 for the idt72t40118 with an 40-bit bus width. in fwft mode, the fifos can be connected in series (the data outputs of one fifo connected to the data inputs of the next) with no external logic necessary. the resulting configuration provides a total depth equivalent to the sum of the depths associated with each single fifo. figure 32 shows a depth expansion using two idt72t4088/72t4098/72t40108/72t40118 devices. care should be taken to select fwft mode during master reset for all fifos in the depth expansion configuration. also, the devices must be operating in single data rate mode since that is the only mode available in fwft. the first word written to an empty configuration will pass from one fifo to the next ("ripple down") until it finally appears at the outputs of the last fifo in the chain ? no read operation is necessary but the rclk of each fifo must be free-running. each time the data word appears at the outputs of one fifo, that device's or line goes low, enabling a write to the next fifo in line. for an empty expansion configuration, the amount of time it takes for or of the last fifo in the chain to go low (i.e. valid data to appear on the last fifo's outputs) after a word has been written to the first fifo is the sum of the delays for each individual fifo: (n ? 1)*(4*transfer clock) + 3*t rclk where n is the number of fifos in the expansion and t rclk is the rclk period. note that extra cycles should be added for the possibility that the t skew1 specification is not met between wclk and transfer clock, or rclk and transfer clock, for the or flag. the "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. there will be no delay evident for subsequent words written to the configuration. the first free location created by reading from a full depth expansion configuration will "bubble up" from the last fifo to the previous one until it finally moves into the first fifo of the chain. each time a free location is created in one fifo of the chain, that fifo's ir line goes low, enabling the preceding fifo to write a word to fill it. for a full expansion configuration, the amount of time it takes for ir of the first fifo in the chain to go low after a word has been read from the last fifo is the sum of the delays for each individual fifo: (n ? 1)*(3*transfer clock) + 2 t wclk where n is the number of fifos in the expansion and t wclk is the wclk period. note that extra cycles should be added for the possibility that the t skew1 specification is not met between rclk and transfer clock, or wclk and transfer clock, for the ir flag. the transfer clock line should be tied to either wclk or rclk, whichever is faster. both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain. figure 32. block diagram of 32,768 x 40, 65,536 x 40, 131,072 x 40, 262,144 x 40 depth expansion in single data rate mode dn input ready write enable write clock wen wclk ir data in rclk read clock rclk ren oe output enable output ready qn dn ir gnd wen wclk or ren oe qn read enable or data out transfer clock 5995 drw35 n n n fwft fwft fwft idt 72t4088 72t4098 72t40108 72t40118 rcs read chip select rcs idt 72t4088 72t4098 72t40108 72t40118
corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com 52 ordering information plastic ball grid array (pbga, bb208-1) commercial (0 c to +70 c) industrial (-40 c to +85 c) low power 5995 drw36 commercial only commercial only commercial and industrial commercial only 4 5 6-7 10 idt xxxxx device type x power xx speed x package x process / temperature range blank i (1) 72t4088 16,384 x 40 ? 2.5v high-speed terasync tm ddr/sdr fifo 72t4098 32,768 x 40 ? 2.5v high-speed terasync tm ddr/sdr fifo 72t40108 65,536 x 40 ? 2.5v high-speed terasync tm ddr/sdr fifo 72t40118 131,072 x 40 ? 2.5v high-speed terasync tm ddr/sdr fifo clock cycle time (t clk ) speed in nanoseconds bb l note: 1. industrial temperature range product is available for 6-7ns as a standard product. all other speed grades are available by sp ecial order. datasheet document history 03/01/2002 pgs. 1, 4, 6, 8, 9, and 23. 04/08/2002 pgs. 1, 8, 9, 11, 33-37, 42, 46-48, and 51. 04/24/2002 pgs. 19, and 28. 05/24/2002 pgs. 6-9, and 12. 11/21/2002 pgs. 1, and 10. 02/11/2003 pgs. 7, 8, and 27. 03/20/2003 pgs. 25, 27, 28, and 44. 12/17/2003 pgs. 10, 31-34, 36-38, 44, and 49. 09/21/2004 pgs. 1, 3, 9-11, 17, and 28.

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